Manufacturing method of gate-last semiconductor device
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as low annealing temperature, source/drain ion activity degradation, and reduced device performance, so as to improve performance and reduce Effect of vacancy defect and stress prevention
Active Publication Date: 2021-03-09
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology
At present, the high-k gate dielectric / metal gate technology includes a gate-front (Gate First) process and a gate-last (Gate Last) process. The gate-last process is usually formed after the source and drain regions are formed by a gate replacement process. Gate dielectric layer and metal gate stack structure, but the annealing temperature of the annealing step used to eliminate high-K gate dielectric defects in this process is usually lower than the annealing temperature of the source-drain ion activation thermal annealing process, which will cause the originally activated source The activity of leaked ions is degraded or even lost, which seriously reduces the performance of the device
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[0030] The existing gate-last process is generally: first form a silicon dioxide gate dielectric / dummy gate structure on the surface of the semiconductor substrate; then complete the source / drain ion in the semiconductor substrate on both sides of the silicon dioxide gate dielectric / dummy gate structure Implantation and annealing activation process; after that, the silicon dioxide gate dielectric / dummy gate is removed through CMP planarization and etching to form a gate groove; then the high-K gate dielectric is redeposited, and a spike annealing treatment is performed to reduce the high-K gate dielectric Defects such as oxygen vacancies in the layer improve the compactness of the high-K gate dielectric layer; then a metal gate is formed on the high-K gate dielectric layer of the gate groove, thereby completing the preparation of the high-K gate dielectric / metal gate semiconductor device. The advantage of this gate-last process is that the metal gate is formed after the source / ...
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The invention provides a method for manufacturing a gate-last semiconductor device. After the first annealing for eliminating defects in the high-K gate dielectric layer, firstly, an oxygen-rich material layer and an absorber are sequentially formed on the surface of the high-K gate dielectric layer. Oxygen material layer, and perform the second annealing, during the second annealing process, part of the oxygen in the oxygen-rich material layer diffuses into the high-K gate dielectric layer, thereby reducing the amount of oxygen in the high-K gate dielectric layer Oxygen vacancy defects ensure the performance of the high-K gate dielectric layer, and the oxygen-absorbing material layer can absorb oxygen in the oxygen-rich material layer, preventing excessive oxygen from diffusing into the high-K gate dielectric layer and the interlayer dielectric layer to make the interlayer dielectric layer thicker, which affects device performance; secondly, after removing the oxygen-absorbing material layer and the oxygen-rich material layer, perform the third annealing to reactivate the activity of the source-drain region ions and reduce the source-drain region resistance, improving the performance of the transistor.
Description
technical field [0001] The invention relates to the technical field of semiconductor device manufacturing, in particular to a method for manufacturing a gate-last semiconductor device. Background technique [0002] With the rapid development of integrated circuits, gate length and silicon dioxide (SiO 2 ) The thickness of the gate oxide layer continues to decrease, the reliability of the gate dielectric layer, the depletion effect of the polysilicon gate, the pinning of the Fermi level, the excessively high gate resistance, and the severe boron penetration are becoming more and more serious, which seriously restricts semiconductor devices. As the characteristics are further improved, a gate stack structure combining a gate dielectric layer of a high-k material with a low equivalent oxide thickness (EOT, Equivalent Oxide Thickness) and a metal gate is widely used. At present, the high-k gate dielectric / metal gate technology includes a gate-front (Gate First) process and a ga...
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IPC IPC(8): H01L21/8238
CPCH01L21/823814H01L21/823821H01L21/823857
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP