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Split-gate power DMOS device

A shielding gate and power technology, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve the problems of increasing the threshold voltage of power DMOS devices, unable to prevent the parasitic BJT from being turned on, and unable to infinitely reduce the resistance of the parasitic BJT base area, so as to improve the resistance UIS invalidation ability, UIS tolerance improvement, effect of preventing opening

Active Publication Date: 2018-07-31
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method cannot prevent the opening of the parasitic BJT, and it cannot avoid the active failure mode of the device UIS caused by avalanche breakdown; in addition, it can only be reduced to a certain extent by high-energy boron implantation or deep diffusion. The base resistance cannot infinitely reduce the base resistance of the parasitic BJT, otherwise it will increase the threshold voltage of the power DMOS device

Method used

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Examples

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Embodiment 1

[0026] A shielded gate power DMOS device, the cross-sectional schematic diagram of its cell structure is as follows figure 2As shown, it includes: a metallized drain 1, a first conductivity type semiconductor substrate 2, a first conductivity type semiconductor drift region 3 and a metallization source 12 stacked in sequence from bottom to top, the first conductivity type semiconductor There are trench gate structures on both sides of the top layer of the drift region 3, and the trench gate structure includes a shield gate electrode 9 disposed at the bottom of the trench 7, a control gate electrode 8 disposed at the top of the trench 7, and a shield gate electrode 8 disposed on the control gate electrode 8. and the dielectric layer 10 around the shielding gate electrode 9, and the control gate electrode 8 and the shielding gate electrode 9 are separated by the dielectric layer 10; there are second trench gate structures between the top layer of the first conductivity type semi...

Embodiment 2

[0028] A shielded gate power DMOS device, the three-dimensional schematic diagram of its cell structure is as follows image 3 as shown, Figure 4 and Figure 5 The cross-sectional schematic diagrams obtained along the line AA' and BB' of the cell structure respectively include: a metallized drain 1 stacked in sequence from bottom to top, a first conductivity type semiconductor substrate 2, a first conductivity type Semiconductor drift region 3 and metallized source 12, both sides of the top layer of the first conductivity type semiconductor drift region 3 have a trench gate structure, and the trench gate structure includes a shielding gate electrode 9 and a device at the bottom of the trench 7 The control gate electrode 8 on the top of the trench 7 and the dielectric layer 10 arranged around the control gate electrode 8 and the shielding gate electrode 9, the control gate electrode 8 and the shielding gate electrode 9 are all along the image 3 The shown x-axis direction ex...

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Abstract

The present invention provides a split-gate power DMOS device, belonging to the technical field of semiconductor power devices. The split-gate power DMOS device is improved based on a traditional split-gate power DMOS device, a top layer of a drift region between trench gate structures at two sides of the device has a body region, the top layer of the body region has source regions and contact regions which are in alternating arrangement, the alternating arrangement direction of the resource regions and the contact regions is reasonably arranged and a heavily-doped current guidance layer is introduced between side walls of the contact regions and a trench to form a current channel with low on resistance and allow the source regions to be in direct contact with a dielectric layer at the side wall of the trench. According to the invention, an avalanche breakdown current is fixed in the current guidance layer and is guided to directly flow away from the contact regions via the current guidance layer without passing through the body region below the source region so as to avoid starting of a parasitic BJT (Bipolar Junction Transistor) and improve the UIS (Unclamped Inductive Switching)tolerance and UIS resistance failure capacity of the device. Besides, the lateral effect of depletion of a split-gate electrode can avoid negative influence of the current guidance layer on the device pressure-resistant property.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor devices, and in particular relates to a shielded gate power DMOS device. Background technique [0002] Power DMOS plays an important role in the field of power conversion because of its advantages such as fast switching speed, low loss, high input impedance, low driving power, and good frequency characteristics. Continuously improving system performance requires power DMOS to have lower power loss and higher reliability under high electrical stress. In order to improve the performance of DMOS, new structures such as floating island unipolar devices and shielded gates (Split-gate) have been proposed. Floating island unipolar device through the N - The P-type voltage divider island is added to the epitaxial layer, so that the maximum electric field in the drift region is divided into two parts. Under the same doping concentration of the epitaxial layer, the breakdown voltage is improve...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/423
CPCH01L29/4236H01L29/7813
Inventor 任敏杨梦琦李佳驹李泽宏高巍张金平张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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