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HKMG-contained NMOS and PMOS integrated manufacturing method

A technology of manufacturing method and process method, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as electrochemical reaction defects, achieve the effects of reducing defects, improving reliability, and increasing the process window

Inactive Publication Date: 2018-08-10
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the change of the material brings about the change of the potential, and the subsequent chemical mechanical polishing process will easily produce electrochemical reaction defects.

Method used

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  • HKMG-contained NMOS and PMOS integrated manufacturing method
  • HKMG-contained NMOS and PMOS integrated manufacturing method
  • HKMG-contained NMOS and PMOS integrated manufacturing method

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Embodiment Construction

[0040] Such as figure 1 Shown is the flow chart of the manufacturing method of the embodiment of the present invention HKMG; as Figure 2A to Figure 2F As shown, it is a device structure diagram in each step of the method of the embodiment of the present invention. The integrated manufacturing method of NMOS and PMOS with HKMG in the embodiment of the present invention includes the following steps:

[0041] Step 1, such as Figure 2A As shown, the process before the metal gate is completed on the semiconductor substrate by using the process method of the pseudo polysilicon gate.

[0042] The process before the metal gate is the same as the existing steps, which are described as follows:

[0043] figure 1 In the figure, the NMOS formation area is the area 201 on the left side of the AA line, and the PMOS formation area is the area 202 on the right side of the AA line. The technology nodes of the NMOS and the PMOS are below 22nm.

[0044] In the embodiment of the present in...

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PUM

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Abstract

The invention discloses an HKMG-contained NMOS and PMOS integrated manufacturing method. The HKMG-contained NMOS and PMOS integrated manufacturing method comprises the steps of completing previous process of a metal gate by employing a pseudo poly-silicon gate process; removing a groove, corresponding to the metal gate, formed in a pseudo poly-silicon gate; forming a first work function layer of aPMOS; removing a first work function layer of an NMOS formation region; forming a first material layer which completely fills each groove and extends out of each groove; opening the top of a groove in a PMOS formation region, and etching the first material layer of an opening region to a position lower than the top of the groove; removing the exposed first work function layer of the opening region by taking the first material layer as a mask, and forming a horn structure in the groove of the PMOS formation region; removing the first material layer; forming a second work function layer of an NMOS; forming an aluminum layer; and performing a chemical and mechanical grinding process. By the HKMG-contained NMOS and PMOS integrated manufacturing method, the filling defect of the metal grate can be reduced, and the device reliability is improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing method, in particular to an integrated manufacturing method of NMOS and PMOS with a high dielectric constant metal gate (HKMG). Background technique [0002] In the HKMG process, it is necessary to form a high dielectric constant (HK) gate dielectric layer and form a metal gate at the same time. In the existing HKMG process, the metal gate last process is usually used. In the metal gate last process, a dummy polysilicon gate is usually required. That is, the pseudo-polysilicon gate, which uses the pseudo-polysilicon gate to form the gate dielectric layer, channel region, and source-drain region of the device, and then replaces the metal gate, that is, removes the pseudo-polysilicon gate, and fills the removed area of ​​the pseudo-polysilicon gate with metal Form a metal grid. [0003] In the existing metal gate last process, usually after the dummy polysilicon gate is removed, a...

Claims

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Application Information

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IPC IPC(8): H01L21/8238
CPCH01L21/823828
Inventor 钮锋王昌锋廖端泉
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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