Strain PMOSFET with surface stress modulation structure

Abstract

The invention discloses a strain PMOSFET with a surface stress modulation structure, and belongs to the technical field of semiconductors. The strain PMOSFET comprises a semiconductor substrate, a gate oxide layer, a grid, a source, a drain and two heavily-doped regions, wherein the gate oxide layer and the gate are sequentially arranged on the semiconductor substrate from bottom to top; the two heavily-doped regions are arranged in the semiconductor substrate and are located on the two sides of the gate; the two heavily-doped regions are respectively a source region and a drain region; the source is arranged on the source region; the drain is arranged on the drain region; at least one insulating medium layer is further arranged on the semiconductor substrate; the insulating medium layer is arranged on one side, far away from the grid, of the heavily-doped region and is adjacent to the heavily-doped region; and a strain cap layer covers the upper surface of the whole device. Accordingto the strain PMOSFET, through a groove-shaped structure between the insulating medium layer and the grid, the decrease of the PMOSFET performance caused by a tensile strain silicon nitride cap layeris inhibited; and the strain PMOSFET is applied to a CMOS with the tensile strain silicon nitride cap layer, so that etching of the tensile strain cap layer on the surface of the PMOSFET is also avoided, and the process complexity is reduced.

Description

technical field [0001] The present invention relates to semiconductor technology, in particular to a strained metal oxide semiconductor field-effect transistor (MOSFET, metal oxide semiconductor Field-Effect Transistor), specifically a strained PMOSFET with a surface stress modulation structure. Background technique [0002] With the development of integrated circuits, the size of devices has become smaller and smaller, and the method of improving the performance of silicon-based MOSFETs (metal oxide semiconductor field effect transistors) by proportional reduction is subject to more and more physical and technological limitations. Under the small-scale manufacturing process, the strained silicon (Strained Silicon, SSi) technology can greatly improve the carrier mobility of the device through the introduction of stress, so that the output current of the device can be increased, thereby improving the performance of the circuit, and can Compatible with the existing Si process,...

AI Technical Summary

Problems solved by technology

In the manufacture of CMOS integrated circuits, a tensile-strained silicon nitride capping layer is often deposited on the chip surface to improve the performance of NMOSFETs, but this capping layer often causes degradation of PMOSFET performance. figure 1 shown

In order to avoid the problem of PMOSFET performance degradation caused by the tensile strained silicon nitride capping layer, the industry generally adopts selective etching to remove the tensile strained silicon nitride capping layer on the surface of the PMOSFET to solve this problem. The CMOS cross-section of the strained silicon nitride capping layer is shown in figure 2 As shown, but this method also brings the problem of increased process complexity, which directly leads to an increase in process cost and a decrease in yield

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