Circuit structure for accelerating convolutional layer and fully connected layer of neural network

A fully connected layer, neural network technology, applied in the field of integrated circuit design, can solve the problem of redundant chip area, and achieve the effect of reducing chip area, improving utilization rate, and improving work efficiency

Active Publication Date: 2018-08-17
FUDAN UNIV
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Problems solved by technology

However, more than 90% of the calculations of the convolutional neural network are in the calculation of the convolutional layer and the fu

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  • Circuit structure for accelerating convolutional layer and fully connected layer of neural network
  • Circuit structure for accelerating convolutional layer and fully connected layer of neural network
  • Circuit structure for accelerating convolutional layer and fully connected layer of neural network

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Embodiment Construction

[0024] In the present invention, the basic block diagram of the circuit that can accelerate the convolutional layer and the fully connected layer at the same time is as follows: figure 1 shown. The working process of the design is as follows: input the features and corresponding weights of each layer, and store them in the external memory (DRAM) described in claim 5 . First, the feature / weight prefetching module reads the features and weights that will be involved in the operation from the external memory and puts them into the local cache. The new data will replace the old and no longer used data in the local cache; then, the control circuit will take out the features and weights that will be involved in the calculation from the local cache according to the order of operations, and send them to the matrix operation unit. After rearranging the features and weights, the operations of the convolutional layer and the fully connected layer are mapped to a series of matrix operat...

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Abstract

The invention belongs to the technical field of integrated circuit designs and particular relates to a circuit structure capable of simultaneously accelerating a convolutional layer and a fully connected layer. The circuit structure comprises five parts: a characteristic/weight pre-fetching module for data reading, a local cache for improving a data reuse rate, a matrix operation unit for realizing matrix multiplication, a temporary data accumulation module for accumulating temporary output results and an output control module in responsible for data rewriting. According to the circuit, a special mapping method is adopted, and operations of the convolutional layer and the fully connected layer are mapped to the matrix operation unit with a fixed size. In the circuit, the memory layout modes of characteristics and weights are adjusted so as to greatly improve the access efficiency of the circuit. Meanwhile, the assembly line mechanism is adopted for scheduling of a circuit module so that all hardware units in each clock period are in a working state, the utilization rate of the hardware units is improved and the working efficiency of the circuit is improved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to a circuit structure for accelerating convolutional layers and fully connected layers of neural networks. Background technique [0002] In the 1960s, Hubel and others proposed the concept of receptive field through the study of cat visual cortical cells. In the 1980s, Fukushima proposed the concept of neurocognitive machine based on the concept of receptive field, which can be regarded as The first implementation of the convolutional neural network, the neurocognitive machine decomposes a visual pattern into many sub-patterns (features), and then enters the hierarchically connected feature plane for processing. It attempts to model the visual system. It enables it to complete the recognition even when the object is displaced or slightly deformed. [0003] Convolutional Neural Networks are a variant of Multilayer Perceptrons. It was developed from th...

Claims

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Application Information

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IPC IPC(8): G06N3/063
CPCG06N3/063
Inventor 韩军蔡宇杰曾晓洋
Owner FUDAN UNIV
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