Physical memory management method and device for embedded real-time system

Abstract

The embodiment of the invention discloses a physical memory management method and device for an embedded real-time system. The method comprises the following steps that: when physical memory indication information which indicates the insufficient physical memory of an application to be operated is obtained, on the basis of a preset address conversion rule, obtaining a mapping relationship betweenthe virtual address and the physical address of a second operation memory, wherein the physical memory indication information is to operate the application to be applied in a first operation memory; and on the basis of the obtained mapping relationship between the virtual address and the physical address of the second operation memory, obtaining a new TLB (Translation Lookaside Buffer) corresponding to the application to be operated and the virtual address of the second operation memory so as to manage the operation of the application to be operated in the second operation memory. Obviously, under the kernel mode of an MIPS (Million Instructions Per Second) framework, the method carries out address mapping relationship conversion on the second operation memory and carries out address update on the current operation address of the application to be operated, a large physical space is managed under the kernel mode, and the problem in the prior art that only a small memory space can be accessed is overcome.

Description

technical field [0001] The present application relates to the field of computer technology, in particular to a physical memory management method and device for an embedded real-time system. Background technique [0002] With the development of science and technology, electronic devices such as computers, mobile phones, and tablet computers are more and more widely used. At present, CPUs based on non-interlocked pipeline-level microprocessors (Million Instructions Per Second, MIPS) in electronic devices can run on On the two priority levels of user state and core state. Taking Godson's 32-bit CPU as an example, the program address space is divided into four large areas: kuseg, kseg0, kseg1 and kseg2, such as figure 1 shown. [0003] kuseg: The virtual space 0x00000000-0x7FFFFFFF (low-end 2G) is an address available in user mode. When the electronic device has a memory management unit (Memory Management Unit, MMU), the segment address needs to be mapped (or translated) by t...

AI Technical Summary

Problems solved by technology

[0009] The embodiment of the present application provides a physical memory management method and device for an embedded real-time system, which solves the problem of small physical memory space accessible by the prior art in the core state through address conversion and address replacement

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