34 results about "Million instruction per second" patented technology

The invention relates to a special ASIC (Application Specific Integrated Circuit) chip system for spaceflight. The special ASIC chip system comprises a MIPS (Million Instructions Per Second) nucleus, a PCI (Programmable Communications Interface) bus interface, an ISA (Internet Security And Acceleration) bus interface, a 1553B bus terminal interface, a 1553B protocol processor, a network interface, a CAN (Controller Area Network) interface, an EMI (External Memory Interface), AD acquisition control logic, OC door control logic, UART (Universal Asynchronous Receiver/Transmitter) serial port, PWM (Pulse Width Modulation) interface, a pulse counter PPC, PCM (Pulse Code Modulation) telemetry remote control module and a general input/output module, wherein the MIPS nucleus, the PCI bus interface, the ISA bus interface, the 1553B bus terminal interface, the 1553B protocol processor, a network interface, the CAN interface and the EMI are connected to an AMBA AXI (Advanced Microcontroller Bus Architecture Advanced eXtensible Interface) bus; and the AD acquisition control logic, the OC door control logic, the UART serial port, the PWM interface, the pulse counter PPC, the PCM telemetry remote control module and the general input/output module are connected to an AMBA APB (All Points Bulletin) bus; and the AMBA AXI bus is connected with the AMBA APB bus through an AXI/APB bridge.

The invention provides a method for realizing operation of an X86 VBIOS (video-bios) on an MIPS (million instructions per second) framework. The method comprises the following steps: a vga_bios_init (void) function reads video-bios and sends the video-bios into an X86 simulator; the X86 simulator simulates a local video memory address 0xa0000; the X86 simulator simulates a video card bios address 0xc0000; the X86 simulator simulates an X86 CPU (central processing unit) register and instructions; the X86 simulator simulates an INT10 interrupt vector; and the X86 simulator simulates sys bios. Through the invention, the display requirements of a Loongson blade are met.

The invention provides a singlechip vehicle failure diagnostic apparatus which is mainly characterized in that a C8051F020 singlechip is selected as a CPU, a CIP-51 microprocessor core completely compatible with an MCS-51 command set is adopted in the CPU, and the peak valve reaches 2MIPS (Million Instructions Per Second). Meanwhile, nearly all analog and digital peripheries and other function parts including a PGA (Professional Graphics Adapter), an ADC (Analog to Digital Converter), a DAC (Digital to Analog Converter), a voltage comparer, a voltage inference, a temperature sensor, an SMBus/I2C, an UART (Universal Asynchronous Receiver Transmitter), an SPI (Serial Peripheral Interface), a timer, a programmable counter and a timer array required by a singlechip data acquisition or control system are integrated in one chip. The invention has the advantages of being capable of realizing that parameters of different electric control systems are measured, reading failure codes of a vehicle-mounted computer, and testing an executer, and has the characteristics of low power consumption, high accuracy, convenience of carrying, and the like.

The embodiment of the invention discloses a physical memory management method and device for an embedded real-time system. The method comprises the following steps that: when physical memory indication information which indicates the insufficient physical memory of an application to be operated is obtained, on the basis of a preset address conversion rule, obtaining a mapping relationship betweenthe virtual address and the physical address of a second operation memory, wherein the physical memory indication information is to operate the application to be applied in a first operation memory; and on the basis of the obtained mapping relationship between the virtual address and the physical address of the second operation memory, obtaining a new TLB (Translation Lookaside Buffer) corresponding to the application to be operated and the virtual address of the second operation memory so as to manage the operation of the application to be operated in the second operation memory. Obviously, under the kernel mode of an MIPS (Million Instructions Per Second) framework, the method carries out address mapping relationship conversion on the second operation memory and carries out address update on the current operation address of the application to be operated, a large physical space is managed under the kernel mode, and the problem in the prior art that only a small memory space can be accessed is overcome.

The invention discloses a timekeeping method using a mixed clock source. The method includes a hardware clock source selection and a software initialization operation. The hardware clock source selection includes that an internal clock source selects a million instructions per second (MIPS) clock source and is used for Clock Event of a non-zero central processing unit (CPU) in a tickless timekeeping mode, and an external clock source selects a high precision event timer (HPET) clock source and is used for Clock Event and Clock Source in a periodic timekeeping mode, Clock Event of a zero CPU in the tickless timekeeping mode and Clock Source in the tickless timekeeping mode. The software initialization operation includes the steps that 1) CPU initialization is performed; 2) the MIPS clock source is registered as Clock Event by each of CPU cores; 3) the MIPS clock source is registered as Clock Source; 4) system device initialization is performed; 5) the HPET clock source is registered as Clock Event by a non-zero core; 6) the HPET clock source is registered as Clock Source; and 7) dynamic core regulation and automatic frequency conversion mechanisms are started. The method simultaneously supports traditional periodic timekeeping modes and recent tickless timekeeping modes.

Techniques to remove inherited blockiness with a low million instructions per second (MIPs) are provided. In one configuration, a device comprises a processor operative to implement a set of instructions to universally correct blockiness. The processor commandeers the in-loop deblocking filtering engine and universally corrects blockiness, including inherited blockiness, using the in-loop deblocking filtering engine.

The invention discloses a PPI (Point-Point Interaction) network clustering method based on an artificial swarm reproduction mechanism, comprising specific steps of: converting a PPI network into an undirected weighted graph; setting parameters; pre-treating each knot and each edge of the PPI network; calculating a weighted network comprehensive characteristic value of all the knots; initializing queen bees; carrying out a mating flight process; partially searching young bees; optimally selecting the queen bees; and selecting the current fitness and comparing until a global optimum clustering result is output. According to the method disclosed by the invention, the clustering quantity does not be pre-set and can be automatically obtained in a clustering process, so that the subjectivity of artificially setting the clustering quantity is avoided, and the time complexity is obviously reduced. An MIPS (Million Instructions Per Second) database is used for carrying out experiment simulation, a result is closer to a standard database, and indexes including the accuracy, the recall ratio, the operation time and the like are better. Compared with the other clustering methods, the method can automatically determine the clustering quantity by adopting the artificial swarm reproduction mechanism based on the reproduction mechanism, so that the clustering process is realized, and the clustering effect and the calculation efficiency are effectively improved.

The invention discloses an encryption transmission method for an MIPS (Million Instructions Per Second) platform on the basis of an HTTP (Hyper Text Transfer Protocol). By simultaneously carrying out encryption and decryption transformation on a browser side and a WEB server side, data transmitted by the HTTP is enabled to be in a ciphertext form. The encryption transmission method has the advantage of implementing encryption protection on plaintext data transmitted between a browser and a WEB server on the basis of the HTTP.

The invention discloses a method for operating Windows application software on a Linux operating system of a million instructions per second (MIPS) version. The Windows application software can be directly operated on the Linux operating system of the MIPS version by using a high-speed X86 instruction simulation method, a central processing unit (CPU) environment management method, a Windows application programming interface (API) environment management method and the like, a Windows operating system is not required, and revising of source codes of Windows software is not required. With tool software which is designed by using the method, a user can use software, which can be only operated on a Windows platform, on a computer of an MIPS framework as randomly as on an X86 computer in spiteof difference between a bottom-layer hardware platform and an operating system, so that a supporting range of application software by the computer of the MIPS framework is expanded, and the method has a high practical value.

The invention discloses a web site access security audit method for an MIPS (Million Instructions Per Second) platform. Every time when URL (Uniform Resource Locator) access is carried out, a URL access address, a user name, access time, IP (Internet Protocol) address information of an accessor and the like are automatically submitted to an audit server on a background by a browser; meanwhile, an audit viewing system is provided, so that an audit administrator can find safety risks by timely analyzing audit information. The web site access security audit method for the MIPS platform has the advantages that a security audit on access record of a user to a Web site in the MIPS platform is implemented; individual behaviors can be monitored; individuals who carry out illegal operations are timely found. By analyzing audit data, various abnormal operations, such as hacker attack, in a network can be timely found.

The invention discloses a WIFI (Wireless Fidelity) upgrading method and apparatus for an operation system of a vehicle-mounted terminal. The upgrading method comprises the steps that an MIPS (Million Instructions Per Second) establishes a wireless connection with an intelligent terminal storing operation system upgrading files through a WIFI unit; the MIPS sends an upgrading request message to the intelligent terminal for enabling the intelligent terminal to send the operation system upgrading files to the MIPS; the MIPS receives and judges whether an operation system upgrading file for the MIPS and an operation system upgrading file for an MCU (Micro Control Unit) exist in the operation system upgrading files or not; if the operation system upgrading file for the MIPS exists, the MIPS enters an upgrading mode and an operation system of the MIPS is upgraded according to the operation system upgrading file for the MIPS; and if the operation system upgrading file for the MCU exists, the operation system upgrading file for the MCU is sent to the MCU and the MCU is triggered to enter the upgrading mode for enabling the MCU to upgrade an operation system of the MCU according to the operation system upgrading file for the MCU.

A digital control system for an electric motor uses two motor-control DSP's operated in parallel to provide high bandwidth motor control. Each of the two DSP's individually may have a limited processing rate (e.g. about 150 million instructions per second [MIPS]). Parallel operation of the DSP's with efficient cross-communication may facilitate motor control at a high sampling frequency. The high sampling frequency may require processing at a rate greater than the limited processing rate (e.g. greater than 150 MIPS), but the combined DSP's may provide the requisite processing speed.

The invention relates to a timestamp based method for measuring million instructions per second (MIPS) required by an embedded software module. The invention relates to a method for measuring MCU time taken or consumed by execution of an embedded software functional module in medical electronic equipment, and particularly relates to observation of MIPS of the MCU required by execution of a digital filter module in medical electronic products. The method is implemented as firmware in an embedded real-time operation system. The measurement method can be repeatedly used in advanced research and development activities of other medical electronic products carried out by use of the real-time operation system.

The invention discloses an application service device for data clusters, which includes a sequentially connected CPU processor, a system hub chip, an input and output controller and an NPU module, the system hub chip is also connected to an internal memory, and the input and output controller passes PCI- The E channel is connected to the NPU module, and the NPU module is also connected to the data transceiver module in turn, and the data information sent or received by the data transceiver module is converted into a communication protocol conversion module and a communication port that can be recognized by various communication interfaces. It cooperates with the dedicated MIPS architecture NPU; the NPU module is also connected to the alarm module. Through the above principle, the present invention can convert the data format of the information, making it into data that can be recognized by different communication interfaces, and the data compatibility is stronger.