SOI embedded triple gate transistor and manufacturing method thereof

Abstract

The invention discloses an SOI embedded triple gate transistor. The SOI embedded triple gate transistor includes an SOI substrate, wherein a plurality of silicon strips separated by shallow trench field oxygen are formed in the top silicon; a gate groove is formed in a gate formation region of the silicon strips; a metal gate structure is formed in the gate groove and has an embedded triple gate structure, and the silicon strips, covered from two side surfaces and a bottom surface, by the metal gate structure, form a channel region; and a source region and a drain region are formed in the silicon strips at both sides of the metal gate structure. The invention also discloses a manufacturing method of the SOI embedded triple gate transistor. The SOI embedded triple gate transistor and the manufacturing method thereof have the advantages of being able to adjust the channel width according to the device design target, avoiding the disadvantages caused by the existing 3D stereo structure ofthe fin crystal concept, being able to reduce the parasitic capacitance and improve the RC delay, being able to increase the area of the embedded structure and reduce the lattice imperfection of theembedded structure, being able to increase the contact area of the contact hole of the source and drain regions and reduce the contact resistance, and eliminating the problem caused by the aspect ratio of the fin.

Description

Technical field [0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an SOI embedded (Embedded) triple gate transistor. The invention also relates to a method for manufacturing an SOI embedded tri-gate transistor. Background technique [0002] With the continuous development of semiconductor technology, the size of the device will continue to shrink, and the channel length of the metal gate of the fin transistor (FinFET) structure must also be proportionally reduced. When the channel length is reduced, the fin width, that is, the fin width (Fin Width), also needs to be reduced. The ratio of the channel length and the fin width, that is, the channel width, is maintained at greater than or equal to 2.5 to overcome the fin width. Sub-threshold leakage in the center of the body [0003] At the same time, in order to increase the current flow of the fin transistor, the fin height (Fin height) needs to be continuously inc...

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Problems solved by technology

[0009] Since the embedded SiGe epitaxial layer 6 and the embedded SiP epitaxial layer 5 are epitaxially formed after the fin body 2 is etched, the embedded SiGe epitaxial layer 2 is reduced along with the shrinkage of W, that is, the width of the fin body 2 . 6 and the size and width of the embedded SiP epitaxial layer 5 will inevitably shrink, which will affect the epitaxial process of the embedded SiGe epitaxial layer 6 and the embedded SiP epitaxial layer 5, so that the embedded SiGe epitaxial layer 6 and the embedded SiP epitaxial layer 5 The epitaxial uniformity is affected

[0010] At the same time, since the source region and the drain region of the fin transistor are formed on the surface of the corresponding embedded SiGe epitaxial layer 6 or embedded SiP epitaxial layer 5, the contact holes on the top of the source region and the drain region will also be formed on the embedded SiGe epitaxial layer 5. On top of the epitaxial layer 6 or embedded SiP epitaxial layer 5, the narrowing of the width of the embedded SiGe epitaxial layer 6 or embedded SiP epitaxial layer 5 reduces the contact area of ​​the contact hole, which increases the contact resistance of the contact hole

[0011] In addition, as W shrinks, the height of the fin body 2 needs to be increased at the same time, so the aspect ratio of the fin body 2 will be larger, and the larger aspect ratio will make the fin body 2 prone to bending or collapse

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