Oxide semiconductor thin-film transistor and manufacturing method thereof

Abstract

Provided in the invention is an oxide semiconductor thin-film transistor comprising a substrate, a gate electrode arranged on the substrate, a grid insulating layer being arranged on the substrate andcovering the gate electrode, an active layer being arranged on the grid insulating layer and being laminated with the gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode that are separated mutually are arranged on the upper surface and the lateral surface of the active layer and are in contact with the active layer respectively. The grid insulating layer includes a lamination structure including a silicon nitride layer adjacent to the gate electrode and a silicon oxide layer adjacent to the active layer. The total thickness of the grid insulating layer is larger than or equal to 3000 angstroms and is less than or equal to 8000 angstroms; the thickness of the silicon nitride layer is greater than or equal to 2000 angstroms; and the thickness of the silicon oxide layer is greater than or equal to 1000 angstroms; and the ratio of the thickness of the silicon nitride layer to the thickness of the silicon oxide layer is larger than or equal to 2. A phenomenon of forming electrostatic breakdown at the intersection part between the data line and the grid line is prevented by controlling the thicknesses and thickness ratio of the siliconnitride layer and the silicon oxide layer.

Description

technical field [0001] The present invention relates to an oxide semiconductor thin film transistor and a manufacturing method thereof, more particularly, to an oxide semiconductor thin film transistor and a manufacturing method thereof which can improve electrostatic damage between a gate and a source / drain. Background technique [0002] Oxide semiconductor thin film transistors (Oxide TFTs) are currently more and more widely used in high-end displays and large-size OLED panels. Common TFT structures may include bottom-gate TFTs, top-gate TFTs, etc. according to the position of the gate. In traditional bottom-gate TFTs, the gate insulating layer in amorphous silicon TFTs usually uses silicon nitride (SiN x ), generally, the gate insulating layer includes an upper layer and a lower layer, and the upper layer of the gate insulating layer contacting the active layer is formed at a low speed to ensure the compactness of the film and reduce defects, while improving the contact ...

AI Technical Summary

Problems solved by technology

When the via hole is formed by dry etching, charges are continuously accumulated on the gate electrode, source electrode and drain electrode. If the withstand voltage of the gate insulating layer is insufficient, it will be broken down by the electric field, forming electrostatic breakdown (ESD), cause the gate insulating layer to be ineffective

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