67results about How to "Prevent electrostatic breakdown" patented technology

The invention discloses a manufacturing method of an X-ray flat panel detector. The method comprises the following steps: providing a substrate; forming a thin film transistor, a bottom electrode and a conductive element on the substrate, wherein the bottom electrode and the conductive element are electrically connected as a whole through a connecting part; forming a photoelectric conversion element and a top electrode on the bottom electrode; and forming a shading layer above a channel of the thin film transistor and etching the connecting part to disconnect the bottom electrode and the conductive element. According to the method, the bottom electrode (the source) and the conductive element are electrically connected as a whole through the connecting part, and when manufacture of the thin film transistor is completed, static electricity produced by the bottom electrode (the source) is released through the conductive element at the moment when a supporting column contacts or is separated from the bottom surface of the substrate in the subsequent manufacturing process so as to avoid electrostatic breakdown of the thin film transistor.

The present invention provides a substrate liquid processing apparatus and a substrate liquid processing method. It is possible to prevent the occurrence of the electrostatic breakdown caused by the discharge of electric charges in a substrate. According to the invention, in the substrate liquid processing apparatus (1), a substrate liquid processing method, and a computer readable storage medium (48) having a substrate liquid processing program stored therein for performing liquid treatment to the substrate (2), prior to processing a circuit-forming surface of the substrate (2) with a chemical liquid, the substrate liquid processing apparatus performs an anti-static process for an surface opposite to the circuit-forming surface of the substrate (2) by an anti-static liquid, thereby emitting the electric charges on the substrate (2).

The invention provides an antenna, an antenna unit thereof and a wireless communication device equipped with the antenna. The antenna unit comprises a first antenna part which comprises a feeding point and a second feeding point part which comprises at least one earth point, wherein the first antenna part and the second antenna part are mutually separated; the second antenna part at least partially surrounds the first antenna part and a part of the first antenna part is intercoupled with a part of the second antenna part to form a first coupling capacitor. The antenna unit provided by the embodiment of the invention leads current of electrostatic discharge to firstly arrive at the second antenna part without arriving at the first antenna part and affecting the chip on the mainboard which is connected with the feeding point of the first antenna part. Besides, the antenna unit provided by the embodiment of the invention not only realizes the radiating function of the antenna together with the mainboard, but also can effectively improve the efficiency of the antenna.

An optical proximity correction method and a mask making method are provided. The optical proximity correction method includes: providing an initial photolithographic mask pattern including a plurality of main patterns; obtaining a main graphic group from a plurality of main graphics based on an electrostatic prone judgement rule, wherein the main graphic group comprises at least two adjacent maingraphics; setting auxiliary graphics between adjacent main graphics in the main graphics group, wherein the auxiliary graphics includes auxiliary main graphics and auxiliary connecting graphics on both sides of the auxiliary main graphics, and the auxiliary connecting graphics connect the auxiliary main graphics and the main graphics; performing OPC correction on the plurality of main graphics and auxiliary graphics to form main correction graphics from the main graphics and auxiliary correction graphics from the auxiliary graphics, wherein the auxiliary correction graphics comprise auxiliarycorrection main graphics corresponding to the auxiliary main graphics and auxiliary correction connection graphics corresponding to the auxiliary connection graphics. The optical proximity correctionmethod avoids the occurrence of graphic missing angles or bridging damage at opposite cusps of adjacent main correction graphics.

The invention discloses a silicon controlled rectifier used for ESD protection. The silicon controlled rectifier includes a pull-up silicon controlled rectifier, a pull-down silicon controlled rectifier, an isolation resistor, a NMOS transistor and a PMOS transistor. The pull-up silicon controlled rectifier comprises a first N well, which consists of a first P+ implanted region and a first N+ implanted region, and a first P well, which consists of a second P+ implanted region and a second N+ implanted region. The pull-down silicon controlled rectifier comprises a second N well, which consists of a third P+ implanted region and a third N+ implanted region, and a second P well, which consists of a fourth P+ implanted region and a fourth N+ implanted region. In the invention, a voltage clamp structure is formed through a PN diode structure and a well resistance structure which are parasitic on the silicon controlled rectifier; fast response of an ESD pulse and preopening of a protective structure can be achieved. By using the invention, opening speed is fast, weak gate oxide layer can be protected from instant and quick ESD static shock.

The invention relates to the field of displaying, and provides an array substrate, a manufacturing method thereof, a display panel and a display device. The manufacturing method of the array substratecomprises the steps of supplying the array substrate which is provided with a pixel region and a fan-out region; forming a first wiring region, a second wiring region and a suspended region between the first wiring region and the second wiring region in the fan-out region, and connecting the fan-out region with the pixel region; forming a film virtual metal wire in the suspended region; and patterning the film virtual metal wire. Through patterning the film virtual metal wire, accumulated static charges are reduced for preventing static breakdown; and on the other hand, Rubbing Mura in friction orientation of an alignment film is prevented, thereby improving product performance. Furthermore simple operation is realized in removing the film virtual metal wire according to the method. The number of processing procedures of the array substrate and manufacturing cost are reduced.

The present invention prevents electrostatic breakdown attributed to static electricity even in and after a cell cutting step. In a display device which includes a substrate, a plurality of pixels which is formed in a pixel part, a plurality of video lines which applies video voltages to the plurality of pixels, and a video voltage selection circuit which selects the video voltages to be inputted to the pixels and applies the selected video voltages to the predetermined video lines among the plurality of video lines, an electrostatic protective circuit for protecting a pixel part is connected to the plurality of video voltage inputting lines which inputs the video voltages to the video voltage selection circuit, and an electrostatic protective circuit for protecting a peripheral circuit is connected to the lines other than the video voltage inputting lines which is connected to the video voltage selection circuit. The electrostatic protective circuit for protecting the pixel part is connected between the plurality of video voltage inputting lines, and the electrostatic protective circuit for protecting the peripheral circuit is connected between the at least one video voltage inputting line and the line other than the at least one video voltage inputting line, between the plurality of lines other than the video voltage inputting lines, and between the line other than the at least one video voltage inputting line and a reference voltage line to which a reference voltage is applied.

The invention provides an array substrate. The array substrate comprises a first signal line and a second signal line which are arranged on different insulated and spaced layers of a substrate; one end of the first signal line comprises a first conductive part; one end of the second signal line comprises a second conductive part; the first conductive part and the second conductive part are electrically connected through a connecting structure; and the orthographic projections of an area where the first conductive part is located and an area where the second conductive part is located, on the substrate, are at least partially overlapped. Correspondingly, the invention further provides a display device. According to the array substrate, the disconnection between the signal lines can be reduced, so that the effect of connection between different signal lines can be improved.

The invention provides a touch display panel and a touch display device. The touch display panel comprises a touch panel and a display panel, the touch panel comprises a touch area and a non-touch area. A plurality of parallel touch electrodes are arranged in the touch area, a signal line connected with the touch electrodes and at least two GND routing lines are arranged in the non-touch area, theGND routing lines are arranged in the peripheral area of the signal line, and the GND routing lines are electrically connected with the grounding end of an external driving circuit. According to thetouch panel, the electrostatic discharge problem of the touch panel can be solved, and the influence of static electricity on the internal signal lines and the touch electrodes connected with the signal lines is reduced.

The invention relates to a chip chuck which comprises a base and a chip bracket positioned on the surface of the base, wherein the section of the top end part of the chip bracket forms a shape with a narrow upper part and a wide lower part; when a target chip is not arranged on the chip chuck, the width of the upper edge of the top end part is less than the distance between two rows of pins of the target chip, and the width of the lower edge is larger than the distance between two rows of pins of the target chip; the height of the top end part is less than the length of the pins of the target chip; and the base and the chip bracket are made of conductive materials and are both grounded. The invention has the advantages that the provided chip chuck can conveniently earth the pins of the chip fast, avoids electrostatic breakdown and meets the requirement of large-scale production to efficiency.

The invention discloses an array substrate, a manufacturing method thereof and a display panel, and belongs to the technical field of displaying. The array substrate comprises a substrate body; the substrate body is provided with a conduction structure, and the conduction structure comprises overlapped grid lines and data lines; the conduction structure is provided with an insulating structure; apublic electrode layer is formed on the insulating structure; first sunken structures right facing the grid lines and second sunken structures right facing the data lines are arranged at the portion,in a non-display area of the substrate body, in the insulating structure, openings of the first sunken structures and the second sunken structures are all away from the substrate body, and the distance between the bottom faces of the first sunken structures and the grid lines is equal to the distance between the bottom faces of the second sunken structures and the data lines. By means of the arraysubstrate, the manufacturing method thereof and the display panel, the problem that a second capacitor is easily subjected to electrostatic breakdown when there are many electrostatic charges accumulated in the second capacitor is solved, and the manufacturing method of the array substrate and the display panel are used for the array substrate.

The invention relates to an array substrate, a manufacturing method of the array substrate, a display panel and a display device. The array substrate comprises a substrate, first leads, a first insulation layer, second leads and a connection part, wherein the first leads are positioned on the substrate; the first insulation layer is positioned on the first leads; the second leads are positioned on the first insulation layer; at least parts of projections of the first leads and the second leads on the substrate are overlapped; at least one of the first leads and the second leads consists of conductive segments which are arranged at intervals; and the connection part is used for electrically connecting adjacent conductive segments of the first leads or the second leads.

The invention discloses a clamp for mounting a plurality of laser chips. The clamp comprises a substrate and a spring block, a through hole is formed in the surface of the substrate, and an optical positioning point a is arranged above the right side of the top surface of the substrate. An optical positioning point b is arranged below the right side of the top surface of the substrate, and the optical positioning point a and the optical positioning point b are both L-shaped structures. A limiting block a is arranged above the left side of the through hole, a rubber layer is arranged at the bottom end of the limiting block a, and the rubber layer is made of anti-static rubber. A chamfer is arranged at the right side of the rubber layer, and through the chamfer, the surface of the chip can be prevented from being abraded during the chip clamping process. A limiting block b is arranged at the right side of the limiting block a, a spring block is arranged in the middle at the bottom end ofthe through hole, and the limiting block a, the limiting block b and the spring block are all fixed to the back of the substrate. A protruding block is arranged above the interior of the spring blockand can move up and down in the spring block, and a spring is arranged at the bottom end of the protruding block. The clamp has the advantages of being capable of clamping a plurality of chips, and being accurate in positioning and firm in clamping.

The invention relates to a semiconductor photoresist cleaning agent, which comprises alcohol amine, C4-C6 polyol, a solvent, organic base, and an additive. All the components are mixed to form a mixedsolution. Then, a semiconductor wafer containing the photoresist is immersed in the mixed solution, heated to 85 degrees centigrade, immersed for a set period of time, taken out, and dried with high-purity nitrogen. During the photoresist removal process, a resin material in the photoresist is dissolved or decomposed in the mixed solution after the semiconductor wafer containing the photoresist is immersed in the mixed solution, so that a purpose of removing the residual photoresist on the surface of the semiconductor wafer is achieved. At the same time, a conductive layer with a thickness of1.2 [mu]m is formed on the surface of the semiconductor wafer immersed in the mixed solution and has an ability to limit the current and protect electrodes and circuits, thereby achieving functions of preventing a chip surface circuit on a circuit board from being oxidized, and avoiding electrostatic breakdown of the circuit and chipping the edge of the chip.

The invention discloses an anti-static structure of a touch screen, which comprises a protective cover plate. The bottom of the protective cover plate is fixedly connected with an upper anti-static matching plate. A grounding groove is etched in the part, in contact with the protective cover plate, of the upper anti-static matching plate. A cathode conducting layer, an isolation layer and an anodeconducting layer are sequentially connected into the groove of the upper anti-static matching plate from top to bottom, and a liquid crystal display layer is connected to the bottom of the lower anti-static matching plate. Conductive adhesives are coated in the grounding grooves of the upper anti-static matching plate and the lower anti-static matching plate; a plurality of grounding wire slots are uniformly formed in the edges of the upper anti-static matching plate and the lower anti-static matching plate; according to the invention, the anti-static matching plates are arranged above the cathode conducting layer and below the anode conducting layer. The two-way electrostatic breakdown phenomenon is effectively prevented. The thickness of the electrostatic layer is reduced through the grounding groove type design. Meanwhile, the upper anti-static matching plate and the lower anti-static matching plate protect the conductive layer while static electricity is effectively guided out. The functions are diversified.

The invention discloses an adjustment base for clamping a PCB. The adjustment base comprises a window-type frame and the PCB clamped in the window-type frame. The inner-side wall of the window-type frame is provided with grooves, the two ends of the PCB are respectively arranged in the grooves at the left-side wall and the right-side wall of the window-type frame; the window-type frame comprises a sleeve whose openings at two sides are of cavity structures, a dead lever arranged in the inner cavity of the sleeve and slide bars respectively connected with the fixed lever through an elastic member; the window-type frame is provided with a wrapping post; and the elastic member comprises a connecting rod whose opening at one end is of a cavity structure, an adjustment rod slidably arranged in the connecting rod and a spring connecting the adjustment rod with the connecting rod, and the adjustment rod is sleeved by the spring. According to the invention, the adjustment rod is sleeved by the spring to enable the spring to extend only along the axial direction of the adjustment rod so as to limit the spring and prevent the spring from deformation due to stretching.