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Package structure

A technology of packaging structure and packaging layer, which is applied to semiconductor/solid-state device parts, semiconductor devices, electrical components, etc., can solve the problems of increasing the volume of the packaging structure, unable to meet the design requirements of miniaturization, and increasing the number of circuit layers, etc. To achieve the effect of reducing the degree of impact

Active Publication Date: 2020-02-14
POWERTECH TECHNOLOGY INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, limited by the size of the decoupling capacitor element, the volume of the packaging structure will increase, so it cannot meet the miniaturization design requirements
Another way of disposing the decoupling capacitive element is to embed (or hide) it in the circuit carrier. This embodiment will increase the number of layers of the circuit layer or the complexity of the wiring on the circuit carrier, and also cannot meet the needs of small customized design requirements

Method used

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Embodiment Construction

[0050] Figure 1A , Figure 1B , Figure 1D , Figure 1F to Figure 1I is a schematic cross-sectional view of the manufacturing process of the packaging structure according to the first embodiment of the present invention. First, please refer to Figure 1A , providing a circuit carrier 110 provided with a first chip 120 and a second chip 122, 122a, wherein the circuit carrier 110 has a first surface 110a and a second surface 110b opposite to the first surface 110a, and the circuit carrier 110 It includes a first pad 111 and a second pad 112 . The first pads 111 and the second pads 112 are located on the first surface 110 a of the circuit carrier 110 , and the shape, size or quantity of the first pads 111 or the second pads 112 are not limited. For example, the shape of the first pad 111 or the second pad 112 can be a strip shape, a disk shape or a square disk shape. In this embodiment, the first pad 111 may be a ground pad, and the second pad 112 may be electrically connect...

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PUM

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Abstract

The invention provides a packaging structure, which includes a circuit carrier, a first chip, a packaging layer, a capacitor and an electromagnetic interference shielding layer. The circuit carrier includes a first pad and a second pad. The first chip is arranged on the circuit carrier and electrically connected with the circuit carrier. The encapsulation layer is disposed on the circuit carrier to cover the first chip. The capacitor includes a first capacitor electrode and a second capacitor electrode that are electrically separated. The first capacitor electrode and the second capacitor electrode are embedded in the encapsulation layer. The electromagnetic interference shielding layer covers at least the encapsulation layer. The first capacitor electrode and the second capacitor electrode extend from the circuit carrier toward the electromagnetic interference shielding layer. The electromagnetic interference shielding layer is grounded through the first capacitor electrode and the first pad. The second capacitor electrode is electrically connected to the second pad.

Description

technical field [0001] The present invention relates to a packaging structure, in particular to a packaging structure with the effect of electromagnetic interference shielding (EMI Shielding). Background technique [0002] In today's packaging structure, the chip is electrically connected to the circuit carrier through bonding wires (Bondwire) or bumps (Bump), so that electronic signals can be transmitted between the chip and the circuit carrier or between chips. However, some chips, such as communication chips, will generate Electromagnetic Interference (EMI) and affect the operation of other chips (such as: data storage chips) in the package structure, so that the electronic signal transmission process between chips is accompanied by noise , thereby affecting the normal operation of the chip. In addition, under the consideration of power integrity (PI), how to ensure that a stable voltage can be provided to the chips in the package structure, especially when multiple chip...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/552H01L23/64
CPCH01L23/552H01L23/642H01L2224/16227H01L2224/16145H01L2224/48145H01L2224/48227H01L2224/32145H01L2924/3025H01L2924/15311
Inventor 潘吉良周建玮
Owner POWERTECH TECHNOLOGY INC
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