Process fluctuation insensitive enhanced signal transmission switch

Abstract

The invention relates to a process fluctuation insensitive enhanced signal transmission switch, belonging to the technical field of integrated circuit design. The process fluctuation insensitive enhanced signal transmission switch comprises a charge transfer MOSFET S, a gate voltage bootstrap boost circuit, a first NMOS M1, a second NMOS M2, a first PMOS M3, a first capacitor C1 and a second capacitor C2, a charge transfer mirror MOSFET MSR, a first mirror NMOS M1R, a second mirror NMOS M2R, a first mirror PMOS M3R, a current source I1, a voltage source V1 and an error amplifier AE. The advantage of the process fluctuation insensitive enhanced signal transmission switch is to overcome the problems that the signal swing is limited and the common mode charge is susceptible to PVT fluctuationin the signal transmission switch circuit in the prior art; and the process fluctuation insensitive enhanced signal transmission switch can be widely used in various signal processing circuits.

Description

technical field [0001] The invention relates to a charge signal transmission switch for a charge domain pipeline analog-to-digital converter, in particular to an enhanced charge signal transmission switch circuit, which belongs to the technical field of integrated circuits. Background technique [0002] With the continuous development of digital signal processing technology, the digitization and integration of electronic systems is an inevitable trend. However, most signals in reality are continuously changing analog quantities, which need to be transformed into digital signals through analog-to-digital conversion before they can be input into digital systems for processing and control. Therefore, analog-to-digital converters are indispensable in future digital system design. Part. In applications such as broadband communications, digital high-definition television, and radar, systems require analog-to-digital converters with both very high sampling rates and resolutions. ...

AI Technical Summary

Problems solved by technology

Under low voltage conditions, V DS occupied by 20% of V DD There is no room for optimization of the voltage dropout; V CK1n The voltage is the global reference voltage of the chip, and its theoretical maximum value can be V DD , but in practice its maximum value is also limited by the G terminal voltage, and the maximum value of the G terminal voltage can only be the power supply voltage V DD , with obvious restrictions

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