NOR-type floating gate memory and fabrication method thereof

Abstract

The embodiment of the invention provides a NOR-type floating gate memory and a fabrication method thereof. The NOR-type floating gate memory comprises a substrate, a source, a drain, a channel region,a tunneling oxide layer, a floating gate, a side-wall insulation layer, an isolation insulation layer, an interlayer insulation layer, a control gate and word lines, wherein the source, the drain andthe channel are formed on a surface of the substrate, the source and the drain are respectively arranged at two sides of the channel region, the tunneling oxide layer and the floating gate are formedon the channel region, the side-wall insulation layer is formed on a side wall of the floating gate, the isolation insulation layer is formed on the source and the drain, the interlayer insulation layer is formed on the isolation insulation layer, the side-wall insulation layer and the floating gate, the control gate is formed on the interlayer insulation layer, the word lines are formed on the control gate, and the source and the drain are multiplexed to be bit lines. In the NOR-type floating gate memory and the fabrication method thereof, provided by the embodiment of the invention, a contact hole from an active region to the bit lines in a traditional structure is omitted, the device structure is simplified, and the size of each storage unit is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, and in particular designs a NOR type floating gate memory and a preparation method. Background technique [0002] NOR type floating gate memory occupies a major share in the non-volatile memory market due to its advantages of high integration, low power consumption, high reliability and high cost performance. [0003] However, with the development of microelectronics technology, NOR floating gate memory is also facing a series of challenges, such as lower power consumption, faster speed, and higher integration level. [0004] The most advanced process node of the existing NOR floating gate structure is the 45nm process node, and the unit area of ​​each storage device under this node is greater than 0.02um 2 , and each device needs to contain at least one metal contact hole from the active region to the bit line metal connection layer. Contents of the invention [0005] In ...

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Problems solved by technology

[0003] However, with the development of microelectronics technology, NOR floating gate memory is also facing a series of challenges, such as lower power consumption, faster speed, higher integration, etc.

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