Manufacturing method of gate spacer

Abstract

The invention discloses a manufacturing method of a gate side wall, comprising the steps of: forming a gate structure formed by superposing a gate dielectric layer, a polysilicon gate and a hard masklayer on the surface of a semiconductor substrate; and forming a gate structure formed by superposing the gate dielectric layer, the polysilicon gate and the hard mask layer. 2, for a side wall dielectric layer; 3, for a sidewall protection dielectric layer on that surface of the sidewall dielectric lay; 4, carry out that first overall etching on the side wall protection dielectric lay and makingthe side wall protection dielectric layer only on the side of the gate structure; 5, perform second overall etching on that side wall dielectric lay to form a side wall, wherein the retained side wallprotective dielectric layer protects the side surface of the side wall, and the side wall protective dielectric lay and the hard mask layer self-align to expose the top surface of the side wall so asto adjust the height of the side wall; Step 6, removing the reserved side wall protective dielectric layer. The invention can prevent the thickness of the side wall from being thinned, so that the thickness of the side wall is maintained; and the height of the side wall can be adjusted to prevent the formation of excessive horns, thereby facilitating the planarization of the gate structure.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing gate spacers. Background technique [0002] Such as Figure 1A to Figure 1C Shown is a device structure diagram in each step of the existing method; as figure 2 As shown, it is a structural diagram of the side wall 105 formed by the existing method when the horn phenomenon occurs in the follow-up. The manufacturing method of the existing grid side wall 105 includes the following steps: [0003] Step 1, such as Figure 1A As shown, a semiconductor substrate 101 is provided, and a gate structure formed by stacking a gate dielectric layer, a polysilicon gate 102 and a hard mask layer is formed on the surface of the semiconductor substrate 101. [0004] The semiconductor substrate 101 is a silicon substrate. [0005] The hard mask layer is formed by stacking the first nitride layer 103 and the second oxide layer 104 . [...

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Problems solved by technology

[0022] Depend on Figure 1C It can be seen that the thickness of the side wall 105 formed by the existing method cannot be maintained, that is, the thickness of the side wall 105 formed initially Figure 1B On the basis of the sidewall dielectric layer 105 shown, the thickness of the sidewall 105 will be reduced by lateral etching consumption, which will have a certain impact on the source and drain implantation of the subsequent source and drain regions.

Simultaneously, the height of the side wall 105 cannot be adjusted and has a larger value, which will form figure 2 The larger horns shown by the dotted circle 110 are not conducive to the subsequent planarization

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