Electronic package and its manufacturing method

Abstract

An electronic package and its manufacturing method, comprising providing a cladding layer embedded with electronic components, forming a first circuit structure with a circuit redistribution layer on it, and then passing a second circuit structure with a circuit layer through a conductive The components are connected to the first circuit structure, so that the circuit redistribution layer and the circuit layer are produced respectively by using a wafer-level circuit process and a substrate-level circuit process to reduce production costs.

Description

technical field [0001] The invention relates to a semiconductor structure, in particular to a packaging structure and a manufacturing method thereof. Background technique [0002] With the vigorous development of the electronic industry, electronic products are gradually moving towards the trend of multi-function and high performance. In order to meet the packaging requirements of miniaturization of electronic packages, a chip scale package (Chip Scale Package, CSP for short) technology has been developed, which is characterized in that the size of the package is only slightly larger than the chip size. [0003] Figure 1A to Figure 1E It is a schematic cross-sectional view of a manufacturing method of a conventional chip-scale package. [0004] Such as Figure 1A As shown, a thermal release tape 100 is formed on a carrier 10 . Next, placing a plurality of semiconductor elements 11 on the thermal release adhesive layer 100, wherein the semiconductor element 11 has an oppo...

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Problems solved by technology

[0009] However, in the existing manufacturing method of the chip size package 1, the circuit structure 16 is generally manufactured by the wafer-level circuit process to manufacture the circuit redistribution layer 160, and its precision is extremely high, which makes the production difficult

[0010] In addition, in response to the electrical requirements of current electronic products, it is necessary to use a multi-layer (generally three to four) circuit redistribution layer 160 to extend the contact of the semiconductor element 11 (the electrode pad 110) to the size of the chip. The outer surface of the package 1, but the production of each line redistribution layer 160 has the risk of yield loss, resulting in the problem that the production cost of the chip size package 1 remains high

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