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A semiconductor chip packaging device

A chip packaging and semiconductor technology, which is applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve problems such as poor soldering performance, and achieve the effects of increasing yield, increasing area, and improving soldering performance

Active Publication Date: 2020-12-25
NANTONG TONGFU MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The inventors of the present application have found in the long-term research process that in the process of soldering existing semiconductor chip packaging devices (for example, quad flat no-lead package devices, square flat no-lead package devices, etc.), soldering often occurs. A case of poor performance because the leads of existing semiconductor packages have only a small area on the bottom for solder to climb

Method used

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  • A semiconductor chip packaging device
  • A semiconductor chip packaging device
  • A semiconductor chip packaging device

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Embodiment Construction

[0036] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0037] see Figure 1-Figure 2 , figure 1 It is a schematic flow diagram of an embodiment of the semiconductor chip packaging method of the present application, figure 2 for figure 1 A schematic structural diagram of an embodiment corresponding to steps S101-S107, image 3 for figure 1 A schematic structural diagram of another embodiment corresponding to steps S103-S107, Figure 4 for figure 1 A schematic structural diagram of another embodiment correspo...

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Abstract

The present application discloses a semiconductor chip packaging device, comprising: a lead frame, including a first groove extending from a first surface of the lead frame to a second surface, and a first groove extending from the second surface to the first surface. Two grooves, a third groove extending from the second surface to the first surface, wherein the first groove communicates with the second groove to form a through hole, and the third groove is located on the The edge of the lead frame; the chip, electrically connected to the lead frame; the molding layer, the molding compound wraps all or part of the first side of the lead frame and the chip, and the first groove is covered by the The molding compound is filled to form the molding layer; the electroplating layer is arranged on the second surface of the lead frame and extends into the third groove, or the third groove and the second groove. Through the above method, the present application can increase the area of ​​the pins of the semiconductor package device for soldering to climb.

Description

technical field [0001] The present application relates to the technical field of semiconductor chips, in particular to a semiconductor chip packaging device. Background technique [0002] With the rapid development of science and technology, the research and development and production of semiconductor chip packaging devices are constantly developing towards the direction of high density, high performance, high reliability and low cost. As a result, the volume of the semiconductor chip packaging device is continuously reduced, the number of pins arranged on the semiconductor chip packaging device is greatly increased, the distance between the pins is getting smaller and smaller, and the density of the pins is getting higher and higher. [0003] The inventors of the present application have found in the long-term research process that in the process of soldering existing semiconductor chip packaging devices (for example, quad flat no-lead package devices, square flat no-lead p...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495H01L23/31
CPCH01L23/3107H01L23/495H01L23/49541H01L2224/97H01L2924/181H01L2224/16245H01L2224/48091H01L2224/48247H01L2924/00014H01L2924/00012H01L2224/81H01L2224/85
Inventor 石磊
Owner NANTONG TONGFU MICROELECTRONICS CO LTD
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