Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor memory device includes a maintaining circuit, a sensing circuit, an output circuit, and a verification circuit. The maintaining circuit isconfigured to maintain data read from a memory cell array and output the data to a data bus in response to a column selection signal. The sensing circuit is configured to sense the data on the data bus in response to at least one sensing enable signal. The output circuit is configured to output the data sensed by the sensing circuit. The verification circuit is configured to verify an operation margin of the sensing circuit and output a verification result. The timing of the at least one sensing enable signal is set according to the verification result of the verification circuit.

Description

technical field [0001] The present invention relates to a semiconductor storage device, in particular to a method for determining read timing in a NAND flash memory. Background technique [0002] When the NAND flash memory performs a page read operation, it maintains the page data selected in the memory cell array in the page buffer, and then sequentially outputs the data maintained in the page buffer to the outside. In order to increase the data reading speed of NAND flash memory, a known flash memory (such as Japanese Patent Laid-Open No. 2006-302341) reads at a high speed by detecting the current difference between a cell selected from a memory cell array and a reference cell. Get multivalued data. [0003] figure 1 A schematic diagram showing a read operation of a NAND-type flash memory. In a read operation, a page of the memory cell array is selected according to a row address, and data “0” or “1” of the selected page is maintained in the page buffer 10 . For exampl...

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Problems solved by technology

However, the operating environment of the flash memory is different (such as the variation of the power supply voltage or the variation of the operating temperature), and the set margin may not be the most appropriate, so that the correct data cannot be loaded into the I / O circuit 60. Possibility of outputting wrong data

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