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Latch

A technology of latches and inverters, applied in the field of latches, can solve problems such as soft errors and achieve high-speed transmission

Inactive Publication Date: 2018-12-28
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] The advancement of integrated circuit technology nodes has brought many challenges to the reliability of chips, one of which is the soft error caused by single event upset (SEU)

Method used

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Embodiment Construction

[0015] combine figure 1 As shown, the latch has the function of resisting two-bit node flipping, and the figure 1 In the illustrated embodiment, the latch consists of a storage cell, 5 transfer gates, and a four-input clocked Muller C cell. CLK is a clock signal, and CLKB is a clock signal obtained by passing CLK through the primary inverter FX1.

[0016] The storage unit is composed of 8 sets of two-input inverters which are mutually latched. Each set of inverters consists of a PMOS transistor and an NMOS transistor in series, wherein the source of the PMOS transistor is connected to the power supply voltage VDD, the source of the NMOS transistor is grounded, and the drain of the PMOS transistor is connected to the drain of the NMOS transistor. Nodes are denoted as storage nodes. The storage unit has 8 storage nodes S1-S8 in total, which are respectively located in each group of inverters.

[0017] The first group of two-input inverters is composed of a PMOS transistor PM...

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PUM

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Abstract

The invention discloses a latch, which is composed of a storage unit, five transmission gates and a muller C unit controlled by four inputs clock. CLK is a clock signal, and CLKB is a clock signal obtained by CLK through a first-stage inverter FX1. 8 group of two-input inverters are latch each other to form the memory cell, each set of inverters consists of a PMOS transistor and an NMOS transistorin series, wherein the source of the PMOS transistor is connected to the power supply voltage VDD, the source of the NMOS transistor is grounded, and the node whose drain of the PMOS transistor is connected to the drain of the NMOS transistor is recorded as a memory node, and the memory cell has eight memory nodes S1 to S8, which are respectively located in each group of inverters. The inventioncan resist the overturning of two-bit nodes and intercept the soft error transmitted by the storage unit.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a latch. Background technique [0002] The advancement of integrated circuit technology nodes has brought many challenges to chip reliability, one of which is the soft error caused by single event upset (SEU). [0003] Soft errors can occur in different electronic devices such as automotive electronics, medical devices, etc. [0004] In recent years, due to the continuous advancement of process nodes, the distance between devices has become closer and smaller, and the size of devices has become smaller and smaller, which makes single event multiple bit flips caused by charge collection and charge sharing an important source of soft errors. Contents of the invention [0005] The technical problem to be solved by the present invention is to provide a latch capable of resisting two-bit node flipping and intercepting soft errors transmitted by storage units. [00...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K3/0233H03K19/003
CPCH03K3/0233H03K19/00338
Inventor 蒋建伟肖军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP