A Design Method of FPGA-Based Yolo Network Forward Reasoning Accelerator

Abstract

The present invention proposes a design method for an FPGA-based YOLO network forward reasoning accelerator, the accelerator includes an FPGA chip and a DRAM, the memory BRAM in the FPGA chip is used as a data buffer, and the DRAM is used as a main storage device; The accelerator design method includes the following steps: (1) Carry out 8-bit fixed-point quantization on the original network data, obtain the position of the decimal point that has the least impact on the detection accuracy, and form a quantization scheme. The quantization process is carried out layer by layer; The nine-layer convolutional network for parallel computing; (3) position mapping. It solves the technical problem that the growth rate of storage resources on the FPGA chip is not as fast as that of the neural network scale in the prior art, and it is difficult to transplant the general target detection network to the FPGA chip according to the traditional design idea, and realizes using less on-chip resources to achieve The purpose of faster speed.

Description

technical field [0001] The invention relates to the technical field of deep learning and hardware structure design, in particular to a design method for forward reasoning acceleration of a target detection network on an FPGA. Background technique [0002] In recent years, machine learning algorithms based on convolutional neural networks (Convolutional Neutral Network) have been widely applied to computer vision tasks. However, for large-scale CNN networks, the characteristics of intensive computation, intensive storage, and large resource consumption have brought great challenges to the above tasks. It is difficult for traditional general-purpose processors to meet the practical requirements in the face of such high computing pressure and large data throughput. Therefore, hardware accelerators based on GPU, FPGA, and ASIC have been proposed and widely used. [0003] FPGA (Field Programmable Gate Array) field programmable gate array is a product of further development on th...

AI Technical Summary

Problems solved by technology

[0005] The existing FPGA-based neural network accelerators often store all the intermediate calculation results of the network layer in the on-chip static memory, and store the weights required by the network in the off-chip dynamic memory. Limits the size of the network that can be accelerated

At this stage, as the requirements for task complexity and precision become higher, the scale of convolutional neural networks is getting larger and larger, and the total number of parameters is also getting larger and larger. However, the process of FPGA chips and the growth of memory resources that can be accommodated on the chip Not so fast, if the previous design method is still followed, the FPGA cannot accommodate a network of this size at all

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