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A fan-out type chip packaging structure and a manufacturing method thereof

A chip packaging structure, fan-out technology, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the high cost of dismantling and bonding risks, not suitable for high-end applications, large RDL line width and line spacing, etc. problems, to achieve the effect of reducing the risk of fragmentation, small warpage, and reducing packaging costs

Inactive Publication Date: 2019-01-15
NAT CENT FOR ADVANCED PACKAGING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In view of the risks and high costs of debonding brought by the carrier board technology used in fan-out packaging in the existing technology, as well as the use of PI process and electroplating process for RDL circuit production, the RDL line width and line spacing are large, which is not suitable for high-end application and other issues, there is an urgent need in this field for a fan-out chip packaging structure and its manufacturing method, which can not only have various advantages of fan-out packaging, but also at least partially overcome the high risk and high cost defects caused by the above-mentioned carrier technology

Method used

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  • A fan-out type chip packaging structure and a manufacturing method thereof
  • A fan-out type chip packaging structure and a manufacturing method thereof
  • A fan-out type chip packaging structure and a manufacturing method thereof

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Embodiment Construction

[0038] In the following description, the present invention is described with reference to various examples. One skilled in the art will recognize, however, that the various embodiments may be practiced without one or more of the specific details, or with other alternative and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the various embodiments of the invention. Similarly, for purposes of explanation, specific quantities, materials and configurations are set forth in order to provide a thorough understanding of embodiments of the invention. However, the invention may be practiced without these specific details. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0039] In this specification, reference to "one embodiment" or "the...

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Abstract

The invention discloses a fan-out type chip packaging structure, comprising: a glass substrate; A conductive through hole arranged inside the glass substrate; A chip arranged on the front face of theglass substrate, the chip is electrically connected to the conductive via hole; A plastic encapsulation layer positioned on the front surface of the glass substrate and covering the chip; A first relayout wiring layer disposed on a back surface of the glass substrate, the first relayout wiring layer being electrically connected to the conductive via; And an external solder ball arranged on the back surface of the glass substrate.

Description

technical field [0001] The invention relates to the technical field of integrated circuit packaging, in particular to a fan-out chip packaging structure and a manufacturing method thereof. Background technique [0002] With the increasing demand for various wearable electronic devices and passive electronic devices, mobile consumer customers need to achieve device miniaturization and higher integration. Therefore, the integration degree of electronic devices is getting higher and higher, and system-in-package (SiP, System-in-Package) is more and more applied to different fields. The advantage of system-in-package is that it can integrate multiple heterogeneous chips or devices, such as active devices, passive devices, chips, MEMS or optical devices, etc., to realize a single package with specific functions, thus forming a system or subsystem. The current integration method is mainly to integrate pre-packaged devices or other sealed heterogeneous chips into a package throug...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/498H01L21/56
CPCH01L23/49827H01L21/56H01L23/3121H01L2924/181H01L2224/16225H01L2924/00012
Inventor 陈峰孙绪燕姚大平林挺宇
Owner NAT CENT FOR ADVANCED PACKAGING
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