IES combined FPGA hardware simulation acceleration system

Abstract

The invention provides an IES combined FPGA hardware simulation acceleration system. The system comprises an IES simulation module, a software and hardware communication module and an FPGA hardware acceleration module. The IES simulation module is used for circularly extracting parallel excitation data designed by the tested FPGA within a preset time period according to a preset simulation clock frequency and sending the parallel excitation data to the FPGA hardware acceleration module; Circularly extracting test data of the FPGA design to be tested from the FPGA hardware acceleration module,converting the test data into a simulation result of the FPGA design to be tested according to a corresponding time sequence and displaying the simulation result. The FPGA hardware acceleration moduleis used for receiving the parallel excitation data and storing the parallel excitation data in the input buffer area; generating a test excitation clock and a working clock of each clock domain designed by the tested FPGA, and driving the input buffer area to output parallel excitation data to the tested FPGA design. Under the action of the parallel excitation data, the tested FPGA is designed tooutput test data to the output buffer area. According to the invention, the operation burden of the simulation environment is reduced, and the FPGA simulation speed is improved.

Description

technical field [0001] The invention relates to an FPGA simulation acceleration system, in particular to the method of combining programmable logic simulation software and FPGA hardware to complete the simulation acceleration of FPGA design, and belongs to the technical field of FPGA simulation testing. Background technique [0002] Simulation verification is a necessary step for FPGA software design and testing, and it is one of the effective means to ensure the quality of FPGA software. Programmable logic gate array (FPGA) devices are used at an ever-increasing scale and design complexity. Conventional FPGA simulation software, such as IES, Modelsim, etc., takes a long time to debug and run in the simulation environment, which cannot fully meet the increasingly intense model development tasks. Therefore, it is necessary to study the simulation verification acceleration technology for FPGA code to meet the application requirements. [0003] At present, there are two ways ...

AI Technical Summary

Problems solved by technology

[0007] (1) The hardware structure is complex, there are special requirements for the accelerator board, and the reusability is not strong;

[0008] (2) The simulation verification software and hardware communication mechanism is not well established, and the design and operation under test cannot be controlled in real time, which limits the application scenarios of simulation acceleration;

[0009] (3) There is no clear control requirement for the hardware operating speed, which is not conducive to FPGA layout and routing operations, and it is prone to timing failures.

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