3D memory device and manufacturing method thereof

Abstract

The invention discloses a 3D memory device and a manufacturing method thereof. The 3D memory device comprises a semiconductor substrate, an array structure, a plurality of channel pillars, a conductive channel and a sealing ring, wherein the array structure is located on the semiconductor substrate and comprises a gate stack structure; the plurality of channel pillars pass through the gate stack structure and are in contact with the semiconductor substrate; the conductive channel passes through the gate stack structure and is in contact with the semiconductor substrate; the sealing ring extends to the semiconductor substrate from the surface of the array structure and surrounds the gate stack structure; the conductive channel includes a first conductive structure filled in a first deep groove; the sealing ring includes a second conductive structure filled in a second deep groove; and the first deep groove and the second deep groove are formed by a synchronous process. According to the3D memory device disclosed in the invention, through forming the first deep groove and the second deep groove by the synchronous process, the problem that a deep hole etching process is incompatible with a deep groove etching process is avoided.

Description

technical field [0001] The present invention relates to memory technology, and more specifically, to a 3D memory device and a manufacturing method thereof. Background technique [0002] The improvement of the storage density of the memory device is closely related to the progress of the semiconductor manufacturing process. As the feature size of the semiconductor manufacturing process becomes smaller and smaller, the storage density of the memory device becomes higher and higher. In order to further increase storage density, memory devices with a three-dimensional structure (ie, 3D memory devices) have been developed. A 3D memory device includes a plurality of memory cells stacked in a vertical direction, which can double the integration level on a wafer per unit area and reduce the cost. [0003] The 3D memory device adopts a stacked structure to provide the gate conductor of the selection transistor and the storage transistor, uses channel pillars to provide the channel ...

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Problems solved by technology

[0004] In the prior art, the sealing ring extends from the surface of the array structure to the semiconductor substrate using a deep groove process, and the electrical connection structure used to connect the semiconductor substrate and external circuits is manufactured using a deep hole process. The sealing ring and the electrical connection structure Formed together in the same process step, however, as the number of layers in the stacked structure increases, the deep hole etching process is not compatible with the deep trench etching process, resulting in the function of the sealing ring not meeting the needs of 3D memory devices

[0005] In addition, the sealing ring formed by depositing metal tungsten in the deep groove through the physical vapor deposition (Physical Vapor Deposition, PVD) process in the prior art will make the fluorine content in the 3D storage device too high (F rich), thereby interfering with the subsequent process. Causes invalidation of 3D memory

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