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A method of making an interconnected inductor

A production method and technology of inductance, applied in the direction of circuits, electrical components, electric solid devices, etc., can solve the problems of size reduction, increase of module area, passive devices cannot be placed on the radio frequency chip, etc., to increase the Q value of inductance, The effect of reducing the size of the inductor

Active Publication Date: 2021-01-08
浙江集迈科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Electronic passive devices include inductors, capacitors, resistors, filters, etc. These passive devices are all analog devices, and their volume cannot be reduced with the reduction of digital circuits. Therefore, for radio frequency chips, it is often encountered Larger passive components cannot be placed on the RF chip, but have to be placed next to the chip, which increases the area of ​​the module

Method used

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  • A method of making an interconnected inductor
  • A method of making an interconnected inductor
  • A method of making an interconnected inductor

Examples

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Embodiment 1

[0039] Such as Figure 1 to Figure 12 As shown, a method for manufacturing interconnected inductors, the specific processing includes the following steps:

[0040] 101) Preliminary processing steps of the first carrier 101: making two rows of TSV holes 102 on the upper surface of the first carrier 101 through an etching process, the two rows of TSV holes 102 are offset from each other to open a hole, and the depth of the TSV holes 102 is smaller than that of the first carrier. The thickness of the carrier board 101. The diameter of the TSV hole 102 ranges from 1um to 1000um, and the depth ranges from 10um to 1000um. An insulating layer is formed by depositing silicon oxide, silicon nitride or direct thermal oxidation on the surface of the first carrier 101 . The insulating layer thickness ranges from 10nm to 100um. The physical sputtering, magnetron sputtering or evaporation process makes the seed layer above the insulating layer. The thickness of the seed layer ranges from...

Embodiment 2

[0047] Such as Figure 13 to Figure 17 As shown, the second embodiment is basically the same as the first embodiment, the difference is that after step 101), a new carrier is bonded with the first carrier 101 to form a new first carrier 101, and the lower surface of the first carrier 101 Thinning exposes the metal post 104, which becomes the upper surface of the new first carrier 101 to be bonded. Among them, thinning can be specifically adopted. First, the lower surface of the first carrier 101 is thinned until there is a certain distance left at the other end of the metal post 104 (the distance is between 1um and 100um), and then the dry etching process continues to reduce the thickness. thin, eventually exposing the metal post 104. The manufacturing method of the second carrier is the same as that of the new first carrier 101 of this embodiment, except that the distribution of the TSV holes 102 is the same as that of the second carrier in the first embodiment.

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Abstract

The present invention discloses a method for manufacturing an interconnected inductor. The method comprises the specific steps of 101) first carrier preliminary processing, 102) first carrier formation, and 103) interconnected inductor formation. The present invention provides a method for manufacturing an interconnected inductor of a three-dimensional inductor embedded in a silicon adapter plate.

Description

technical field [0001] The invention relates to the technical field of semiconductors, and more specifically, it relates to a method for manufacturing interconnected inductors. Background technique [0002] Electronic passive devices include inductors, capacitors, resistors, filters, etc. These passive devices are all analog devices, and their volume cannot be reduced with the reduction of digital circuits. Therefore, for radio frequency chips, it is often encountered Larger passive components cannot be placed on the RF chip, but have to be placed next to the chip, which increases the area of ​​the module. [0003] Especially for inductors, planar structure inductors arranged on the surface of chips or interposer boards occupy a large area, but the Q value of the inductor is relatively small. Contents of the invention [0004] The invention overcomes the disadvantages of the prior art, and provides a method for manufacturing an interconnected inductor embedded in a silico...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/48H01L23/64
CPCH01L21/486H01L23/645
Inventor 冯光建
Owner 浙江集迈科微电子有限公司