A method and device for synchronizing continuous serial data at the same frequency

Abstract

The invention discloses a method and device for synchronizing continuous serial data at the same frequency. The serial data signals sent by the transmitting module are controlled in parallel by several receiving same-frequency clocks with different phases, and several sampling values ​​are obtained. Judgment of each sampling value to obtain the best receiving clock at the same frequency, overcome the problem of single-shot data signal sampling error caused by path delay, time jitter, etc. The big problem is to improve the sampling accuracy of asynchronous signals with the same source and frequency, ensure the correctness of the internal data of the chip, reduce the overhead of the clock tree caused by timing convergence, reduce the cost of the chip, and reduce the area of ​​the chip.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a method and device for synchronizing continuous serial data at the same frequency. Background technique [0002] Existing server chips need to use a large number of algorithm modules. One algorithm module is named module_B, and there will be hundreds of repeated module_B in a chip. When the main control module module_A in the chip communicates with each algorithm module module_B, it needs to involve Synchronous and asynchronous processing of signals. refer to figure 1 , the main control module module_A is connected to the algorithm module module_B, the clock signal CLKA in the main control module module_A and the clock signal CLKB in the algorithm module module_B have the same source and frequency, and when the main control module module_A sends a data signal to the algorithm module module_B, the algorithm module Module_B uses the clock signal CLKB to synchronize three ...

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Problems solved by technology

refer to figure 1 , the main control module module_A is connected to the algorithm module module_B, the clock signal CLKA in the main control module module_A and the clock signal CLKB in the algorithm module module_B have the same source and frequency, and when the main control module module_A sends a data signal to the algorithm module module_B, the algorithm module Module_B uses the clock signal CLKB to synchronize three beats for synchronization processing. When the distance between the main control module module_A and the algorithm module module_B is relatively long, it is more difficult to do synchronization convergence during static timing analysis due to path delay and clock uncertainty. If The main control module module_A and the algorithm module module_B do not converge according to the strict synchronization sequence. When the algorithm module module_B performs 3-beat synchronous asynchronous processing through the clock signal CLKB, the single-shot data signal will also be caused by path delay and time jitter. sampling error

Because both the clock signal and the data signal need to go through a long distance to reach the algorithm module module_B, when the chip scale is large, the phases of the clock signal and the data signal are not fixed, such as figure 2 As shown, when the clock signal is at the transition edge of the data signal, the data signal sampled by the rising edge 1 of the first clock signal may be 1 or 0; the data signal sampled by the rising edge 2 of the second clock signal may be 1 or 0 0, resulting in data sampling error

Because there are many algorithm modules module_B and the chip scale is large, if all the algorithm modules perform full synchronous convergence processing, the consumption of the clock tree needs to be increased, resulting in additional chip cost

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