Method and device for testing logic model in a chip

Abstract

The invention relates to the chip technology, and in particular to a method and a device for testing a logical model in a chip for improving the test efficiency and the fault coverage of the logical model without occupying a large amount of logical resources. The method is as follows: generating a test vector set according to a preset checkerboard format, writing and reading test vectors in the test vector set from an RAM in a logical model to be tested so as to complete a fault test on the RAM, wherein each memory bit is read and written by using two logical values with opposite values in theRAM, so that RAM detection can be realized without reconfiguring an FPGA chip, and the adopted detection circuit is simple in structure, is easy to implement, and occupies fewer logical resources, sothat various types faults of the RAM in the logical model can be detected accurately and comprehensively without without occupying a large amount of logical resources, thereby improving the test efficiency and the fault coverage.

Description

technical field [0001] The invention relates to chip technology, in particular to a method and device for testing logic models in a chip. Background technique [0002] In the existing technology, there are a large number of first-in-first-out (Fisrt InFirst Out, FIFO) models in the data link in the digital communication baseband chip, which are used for flow control back pressure and cross-clock domain processing. The failure of the FIFO model will directly affect the communication Signal transmission, therefore, requires effective means to test the FIFO models in various chips. [0003] At present, the Field-Programmable Gate Array (FPGA) chip is a commonly used digital communication baseband chip. FPGA chip manufacturing is based on the Static Random Access Memory (SRAM) structure, which is flexible and configurable online. Its basic unit is composed of a look-up table (Look-UpTable, LUT), a register (Register), a random-access memory (Random-Access Memory, random-access ...

AI Technical Summary

Problems solved by technology

[0019] However, using the application-related testing method, although different logic models can be tested in a targeted manner, due to the limited number of logic resources, after the logic model is built, the remaining logic resources need to be used to set the boundary scan chain. Therefore, The number of boundary scan chains set is also limited, so that it is impossible to conduct comprehensive coverage tests on all links in the logic model, and it will also take up too many logic resources that can be used for business configuration

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