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Memory and method of forming the same

A memory and area technology, applied in the direction of semiconductor devices, electric solid devices, electrical components, etc., can solve problems affecting memory performance and reliability, memory short circuit, etc., to achieve the effect of improving performance and avoiding short circuit problems

Active Publication Date: 2021-07-20
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, the current memory often has the problem of short circuit between adjacent common source lines, which seriously affects the performance and reliability of the memory

Method used

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  • Memory and method of forming the same

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0023] As mentioned in the background art, the common source lines of the memory in the prior art are prone to short circuit.

[0024] The inventors found that the short circuit between the common source lines of the memory is mainly due to the fact that when the conductive material filled in the common source trenches is planarized, some conductive materials will remain on the top, so that the adjacent common source lines Short circuit between poles.

[0025] In order to solve the above problems, the inventor proposes a new memory and its forming method.

[0026] The specific implementation of the memory provided by the present invention and its forming method will be described in detail below in conjunction with the accompanying drawings.

[0027] Please refer to figure 1 A substrate 100 is provided, and a stacked structure 200 having an array region 201 and a stepped region 202 is formed on the surface of the substrate 100 , the stacked structure 200 includes an insulati...

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Abstract

The present invention relates to a memory and a method for forming the memory. The method for forming the memory includes: providing a base, the base including a substrate, a storage stack structure located on the surface of the substrate, a dielectric layer covering the storage stack structure, Through the common source groove of the dielectric layer and the stack structure, the storage stack structure includes an array area and a stepped area surrounding the array area, the surface of the dielectric layer covering the stepped area has a depression, and the bottom of the depression is lower than Covering the surface of the dielectric layer in the array area; forming a conductive layer that fills the common source groove and covers the dielectric layer; performing a first planarization treatment on the conductive layer to expose the dielectric layer outside the depression performing anisotropic etching on the dielectric layer so that the exposed surface of the dielectric layer is lower than the bottom of the depression; performing a second planarization treatment until the conductive layer remaining in the depression is removed. The performance of the memory formed by the above method is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and pursue lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D or not) flash memory and 3D NAND (3D NAND) flash memory. [0003] Among them, 3D NAND memory takes its small size and large capacity as the starting point, and the design concept of highly integrated storage units stacked in three-dimensional mode is to produce a memory with ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/11524H01L27/11548H01L27/11556H01L27/1157H01L27/11575H01L27/11582H10B41/35H10B41/27H10B41/50H10B43/27H10B43/35H10B43/50
CPCH10B41/50H10B41/35H10B43/50H10B41/27H10B43/35H10B43/27
Inventor 刘慧超张大伟杨俊铖
Owner YANGTZE MEMORY TECH CO LTD