A High-speed Digital Correlated Double Sampling Circuit Structure Based on Monoslope ADC

A technology of digital correlation and circuit structure, applied in TV, electrical components, color TV, etc., can solve problems such as slow speed, limited digital CDS application, long A/D conversion time, etc., to reduce chip area, reduce fixed Pattern noise, the effect of increasing the operating speed

Inactive Publication Date: 2021-05-11
TIANJIN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This causes the single slope ADC in digital CDS to need more ramps, which makes the A / D conversion time of digital CDS much longer than analog CDS
Although digital CDS helps to obtain high-quality images, the speed is much slower than analog CDS, which limits the application of digital CDS

Method used

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  • A High-speed Digital Correlated Double Sampling Circuit Structure Based on Monoslope ADC
  • A High-speed Digital Correlated Double Sampling Circuit Structure Based on Monoslope ADC
  • A High-speed Digital Correlated Double Sampling Circuit Structure Based on Monoslope ADC

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Embodiment Construction

[0020] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0021] Such as figure 1 As shown, the present invention is based on the high-speed digital correlation double sampling circuit structure of single slope ADC, comprising:

[0022] Two comparators U1, U2 for performing A / D conversion operations; comparator U1 is used to compare the reset signal V rst and ramp signal V ramp , comparator U2 is used to compare the exposure signal V sig and ramp signal V ramp

[0023] also includes a holding capacitor C H1 , C H2 and blocking capacitor C 1 , C 2 , wherein, the positive input terminal of comparator U1 and the negative input terminal of comparator U2 are respectively passed through the DC blocking capacitor C 1 , C 2 , and the swit...

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Abstract

The invention discloses a high-speed digital correlation double-sampling circuit structure based on a single-slope ADC, including a comparator U1 and a comparator U2 for performing A / D conversion operations; the comparator U1 is used to compare the reset output from the pixel unit reset Signal V rst and ramp generator to form a ramp signal V ramp , the comparator U2 is used to compare the exposure signal V output from the pixel unit after exposure sig and the ramp generator to form the ramp signal V ramp , between the comparator U1, the comparator U2 and the pixel unit, a holding capacitor C is respectively set H1 , hold capacitor C H2 are respectively used to save the reset signal V output by the pixel unit rst and the exposure signal V sig . The invention can increase the working frequency of the circuit while reducing the fixed mode noise.

Description

technical field [0001] The invention relates to the technical field of CMOS image sensors, in particular to a high-speed digital correlation double-sampling circuit structure based on a single-slope ADC. Background technique [0002] In a CMOS image sensor, due to factors such as process and temperature, there is a certain degree of mismatch between transistors in each column of pixel units, such as changes in the threshold voltage of source followers, fluctuations in the size of MOS transistors, and the like. Under the same lighting condition, the mismatch of these transistors will lead to a deviation in the output value of the pixel unit, and this deviation value forms a fixed pattern noise (Fixed Pattern Noise, FPN) in the pixel unit. Fixed pattern noise is one of the main factors that cause image quality degradation. [0003] Correlated Double Sampling (CDS) technology can eliminate the fixed pattern noise in the pixel, that is, the reset signal V rst and the exposure ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N5/374H04N5/357H04N5/365
CPCH04N25/67H04N25/60H04N25/76
Inventor 高静衡佳伟聂凯明徐江涛史再峰
Owner TIANJIN UNIV
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