A current subtraction circuit and its application
A subtraction circuit and current technology, which is applied in the direction of adjusting electrical variables, instruments, control/regulation systems, etc., can solve the problems that cannot meet the current linear subtraction and large current threshold detection, so as to improve flexibility and adaptability, high-efficiency transmission, Improve the effect of application range
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Embodiment 1
[0044] The first embodiment of the present invention is Figure 1a As shown, in this embodiment, the MOS transistor adopts a PMOS transistor, and the current mirror adopts a common current mirror circuit. The operational amplifier OA1 and the PMOS transistor M1 constitute the first current buffer, and the operational amplifier OA2 and the PMOS transistor M2 constitute the second current buffer. NMOS tubes M3 and M4 form a current mirror circuit, the output current of the first current buffer is directly connected to the output terminal of the current mirror mirror, and the output current of the second current buffer is mirrored to its output by the current mirror composed of M3 and M4 terminal, and finally get the subtraction result I of the two currents at the output terminal of the current subtraction circuit out =I in1 -I in2
[0045] Specifically, the input impedance of the current buffer composed of operational amplifier OA1 and PMOS transistor M1 is
[0046]
[004...
Embodiment 2
[0061] The second embodiment of the present invention is as Figure 1b As shown, it adopts a dual circuit design interchangeable with PMOS and NMOS in Embodiment 1, and its input current is reversed.
[0062] Analyzing Embodiments 1 and 2, since it is necessary to ensure that all MOS tubes work in the saturation region, the reference level of the input terminal in Embodiment 1 is:
[0063] V REF =V GS3 +|V DS2 |
[0064] That is, V REF = DC voltage drop of current mirror + |V DS2 |
[0065] Input end reference level in embodiment 2:
[0066] V REF =V DD -|V GS3 |-V DS1
[0067] That is, V REF =V DD - DC voltage drop of the current mirror - V DS1
[0068] Analysis shows that V in embodiment 1 under the same situation REF higher, the input reference level V in Example 2 REF Low, in advanced CMOS technology low power supply voltage applications can be based on the input level V REF Choose from different needs.
Embodiment 3
[0070] From the analysis in Embodiment 2, it can be known that the output impedance of the entire current subtraction circuit is the parallel connection of the output impedance of the current buffer and the output impedance of the current mirror, and because the output impedance of the current buffer is very large, the impedance after the parallel connection is approximately equal to that of the current mirror The output impedance of , while in Examples 1 and 2 is r o4 , the ordinary current mirror circuit is relatively small, so in this embodiment, a cascode current mirror is used to replace the ordinary current mirror circuit, please refer to Figure 2a , its output impedance is raised to r in the cascode current mirror o5 g m6 r o6 , thereby increasing the output impedance of the current subtraction circuit.
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