Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device includes forming a plurality of bit line structures on a semiconductor substrate, wherein a plurality of trenches are included between the bit line structures. The manufacturing method of the semiconductor device also includes forming a first oxide layer to conformably cover the bit line structure and the trench, and forming a photoresist material layer in the trench and on the first oxide layer, wherein the etching of the photoresist material layer Selectivity is higher than that of the first oxide layer. The manufacturing method of the semiconductor device further includes removing the photoresist material layer to form capacitor contact holes between the bit line structures, and forming capacitor contacts in the capacitor contact holes. The invention can effectively reduce the parasitic capacitance of the semiconductor device, and further increase the capacitance to amplify the signal.

Description

technical field [0001] The present invention relates to a semiconductor device and its manufacturing method, in particular to a dynamic random access memory and its manufacturing method. Background technique [0002] In a dynamic random access memory (DRAM), the signal ΔV released by the capacitor discharge is actually very small, so it must be amplified by a sense amplifier so that the capacitor discharge signal can be sensed and read. However, when the signal ΔV released by the capacitor is too small, the signal cannot be sensed. [0003] Capacitively amplified signals are related to the following equation: [0004] [0005] It can be seen from the above formula that the capacitor amplifies the signal ΔV BL Parasitic capacitance C with the bit line (bit line, BL) BL and DRAM capacitance C S relevant. Among them, increasing the capacitance to amplify the signal ΔV BL One of the ways is to reduce the parasitic capacitance of the bit line. [0006] In current DRAMs,...

AI Technical Summary

Problems solved by technology

However, as the process size continues to shrink, the distance between the bit line and the capacitor contact in DRAM is getting shorter and shorter, and as the capacity demand of DRAM is increasing, the length of the bit line is also getting longer

These will lead to an increase in the parasitic capacitance of the bit line, thereby reducing the capacitively amplified signal ΔV BL

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