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Digital coding circuit and method applied to analog-to-digital converter of ultra-high-speed pipeline folding interpolation structure

An analog-to-digital converter and digital coding technology, which is applied in the direction of analog-to-digital converters, error detection coding using multiple parity bits, analog-to-digital conversion, etc., can solve the problems affecting quantization accuracy, restricting the development of folding interpolation ADC, Process deviation sensitivity and other issues

Active Publication Date: 2019-11-19
HEFEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the folded interpolation ADC adopts a fully open-loop structure, and the zero-crossing point generated by the folded interpolation signal is extremely sensitive to process deviation, which affects the actual quantization accuracy.
In the case of smaller and smaller process feature sizes and lower power supply voltages, the mismatch of analog circuits has become one of the difficulties in circuit design, which also restricts the development of folded interpolation ADCs.

Method used

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  • Digital coding circuit and method applied to analog-to-digital converter of ultra-high-speed pipeline folding interpolation structure
  • Digital coding circuit and method applied to analog-to-digital converter of ultra-high-speed pipeline folding interpolation structure
  • Digital coding circuit and method applied to analog-to-digital converter of ultra-high-speed pipeline folding interpolation structure

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Embodiment Construction

[0059] In this embodiment, the analog-to-digital converter is a seven-stage pipeline composed of a one-stage pre-amplification stage and a six-stage folding interpolation stage, a digital encoding circuit applied to an analog-to-digital converter with an ultra-high-speed pipeline folding interpolation structure, such as figure 1 As shown, including: cycle thermometer code to multi-ary decoding circuit module, multi-ary to binary logic decoder module, serial adder group module;

[0060] The circulation thermometer code-to-multi-ary system decoding circuit module extracts a total of 23 comparator output signals from the 7-stage pipeline of the analog-to-digital converter. Therefore, the encoding circuit in this embodiment only needs 23 comparators, which is greatly improved compared with the traditional folding interpolation ADC. Saves the number of comparators. The output signals of the 23 comparators specifically include: two digital signals output by the first-stage pre-ampli...

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Abstract

The invention discloses a digital coding circuit and a method applied to an analog-to-digital converter of an ultra-high-speed pipeline folding interpolation structure. The circuit comprises a cyclicthermometer code-to-multi-system decoding circuit module, a multi-system-to-binary logic decoder module and a serial adder group module, wherein the cyclic thermometer code-to-multi-system code conversion module comprises recursive clamping correction logic. According to the circuit, the influence of the circuit structure and the process limitation on the ADC quantization precision can be reduced,so that high-speed and accurate digital coding is realized.

Description

technical field [0001] The invention belongs to the technical field of digital coding solutions for analog-to-digital converters in mixed signal circuit design, and specifically relates to a digital coding solution suitable for ultra-high-speed pipeline folding interpolation ADCs. Background technique [0002] With the rise of 5G mobile communications, the European Union has launched the Mobile and Wireless Communications Enablers for the Twenty-Twenty Information Society (METIS) project to establish a new generation of 5G communications standards. The proposed indicators include peak data rates greater than 10Gb / s and wireless delays less than 1 millisecond. In the 5G communication standard proposed by the Ministry of Industry and Information Technology of my country, the speed and accuracy of the ADC are required to reach 3.6Gs / s and 12 bits respectively. Therefore, it is of great significance and value to study high-speed and high-precision ADCs. [0003] There are many st...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/12H03M1/10H03M13/11
CPCH03M1/1205H03M1/1009H03M13/1105Y02D30/70
Inventor 胡逸俊邓红辉饶晨光尹勇生陈红梅
Owner HEFEI UNIV OF TECH