A Novel Structure of Two-step Single-slope Analog-to-Digital Converter

Abstract

The invention belongs to the technical field of analog-to-digital conversion, in particular to a two-step single-slope analog-to-digital converter with a novel structure. In the present invention, by setting the negative terminal input of the comparator 201 as a fixed level V T , the positive terminal input passes through the function of the switched capacitor control circuit 203, so that the positive terminal input includes the input signal V IN , fixed level V T and ramp voltage (coarse ramp voltage V Ramp_Coarse and fine ramp voltage V Ramp_Fine ), so that in each quantization, the comparator 201 is at a fixed level V T Comparing nearby reduces the impact of the comparator input offset voltage and achieves better performance indicators.

Description

technical field [0001] The invention belongs to the technical field of analog-to-digital conversion, in particular to a two-step monoslope analog-to-digital converter with a novel structure. Background technique [0002] An analog-to-digital converter (Analog to Digital Converter, ADC) converts a natural continuous-time, continuous-amplitude analog signal into a discrete-time, discrete-amplitude digital signal, and supplies the subsystem for processing. Various performance indicators of ADC, including resolution, sampling rate, and power consumption, directly affect the processing capability of the entire system. As one of the core modules of electronic system, ADC is a hotspot of electronic system research and design. However, due to the influence of non-ideal factors such as device mismatch, parasitics, coupling, and noise in the actual circuit, as well as the limited circuit area, the actual ADC test results cannot achieve the pre-simulated performance. Therefore, caref...

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Problems solved by technology

[0007] For the above-mentioned two-step single-slope ADC, it can be seen that for different input signals, the comparator is compared near different common-mode levels, and due to the limited common-mode rejection ratio of the comparator, the The input offset of the comparator is related to the input common-mode level; in the multi-stage comparator 101, the input offset storage is used, which requires the comparator to obtain higher gain through larger power consumption, and the above disadvantages will Deteriorating overall metrics for ADCs

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