Grid electrode for improving filling capacity of dielectric layer in zeroth layer and process method

Abstract

The invention discloses a grid electrode for improving a filling capacity of a dielectric layer in a zeroth layer. A plurality of grid electrodes are arranged on a semiconductor substrate, and a certain distance is arranged between the grid electrodes. A section of each grid electrode is in a trapezoid shape, which means that a top width of the section of each grid electrode is smaller than a bottom width. In the invention, each grid electrode with the trapezoidal section is formed to replace a traditional vertical grid electrode design so as to increase an opening distance between groove topsbetween the grid electrodes and reduce a depth-to-width ratio. A problem that the filling capacity is limited in a manufacturing process of the dielectric layer in the zeroth layer is effectively solved, formation of holes is reduced, performance of a device is improved, and a product yield is increased. The process method of the invention is simple and easy to implement.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing technology, in particular to a gate that improves the filling ability of the zeroth inner dielectric layer in the gate-last process of semiconductor manufacturing. [0002] The invention also provides a process method of the gate. Background technique [0003] Complementary metal oxide semiconductor device (CMOS: Complementary Metal-Oxide-Semiconductor) manufacturing technology continues to develop along Moore's law. Increase, below 5nm, due to the tunneling effect of electrons, SiO 2 The leakage current generated as a gate dielectric is no longer acceptable. Replace SiO with high dielectric constant (high-k) dielectric 2 It can be seen that the equivalent silicon dioxide insulation thickness can be effectively reduced, and at the same time, a larger physical thickness of the gate dielectric can be obtained, thereby blocking gate leakage at the source. At present, two processe...

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Problems solved by technology

However, as the size of the device shrinks, limited by the Design Rule, the gap between the gates becomes smaller and smaller, and the aspect ratio of the trench becomes larger, and voids will inevitably be generated during the process of filling the inner dielectric layer ( Void ), in the subsequent process, because the ILD0 at the top of the cavity is relatively thin, it is easily corroded by acid or consumed during regrinding, and an open hole is formed between the two gates, thus losing the isolation function

[0005] In order to improve the filling performance of the ILD0 layer, the ILD0 preparation process with better filling ability, such as the high aspect ratio process (HARP: High Aspect Ratio Process), is generally used. However, since this process directly uses O 2 Thermochemical reaction with TEOS (tetraethyl silicate) without plasma assistance, so voids will still form

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