Method for quickly converging establishment time after gate-level netlist modification

Abstract

The invention discloses a method for quickly converging establishment time after gate-level netlist modification. The method comprises the following implementation steps: taking a function correctionpoint as a gate-level netlist and storing a database to obtain a database A0 and a copy B0; extracting function correction logic from the copy B0 after local time sequence optimization, and rewritingthe function correction logic into an ECO command File1; storing the database A0 into which the File1 is read as a database A1; exporting all units and lines in the File 1 to form a physical file File3; checking and correcting local layout wiring in the database A1 of the read-in file File3, storing the local layout wiring as a database A2, performing parasitic parameter extraction on the database A2, generating a time sequence analysis report according to a time sequence, and outputting the time sequence analysis report. According to the method, the problem of establishment time violation after sign-off front door level netlist function modification is efficiently solved in a short time with less iteration and small investment, a large amount of manpower and time investment is saved, andthe project design time is shortened.

Description

technical field [0001] The present invention relates to the field of back-end physical design of integrated circuits, in particular to a method for rapidly converging and establishing time after gate-level netlist modification, which is used for setting-up time violations caused by gate-level netlist function modification before signoff correction. Background technique [0002] The most important and critical work in the physical design of integrated circuit chips is to do timing analysis. The purpose of each timing analysis is to check whether the current design results meet the clock control and the required constraints. This timing check is a pair of often said setup time and hold time. Timing closure has always been the key point of today's chip design, and it is also the biggest challenge. [0003] Because the physical implementation cycle is very long, the physical design is generally implemented after the register-transfer level (RTL, register-transferlevel) netlist...

AI Technical Summary

Problems solved by technology

[0003]Because the physical implementation cycle is very long, the physical design is generally implemented after the register-transfer level (RTL, register-transferlevel) netlist is frozen, but if the The gate-level netlist function modification occurs before the core (signoff), and timing convergence at this time is a big problem and challenge

At present, the usual solution to such situations in the industry is to restart the physical design, but the physical design of the module (block) needs to be reconsidered, re-estimated, and re-corrected from the top-level point of view. This greatly increases the time cost and labor cost of the project, which in turn affects the chip design cycle

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