A three-dimensional memory and its preparation method, a photolithography mask

Abstract

The embodiment of the present invention discloses a three-dimensional memory and its preparation method, and a photolithography mask; wherein, the three-dimensional memory includes: a plurality of storage unit areas arranged at intervals; filled between the storage unit areas, A filling material layer for electrically isolating each of the memory cell regions; and a stress buffering structure located in the filling material layer, the stress buffering structure is separated from the sidewall of at least one memory cell region by a preset interval The distance is set to buffer the stress effect of the filling material layer on the sidewall of the memory cell region; wherein, the stress buffer structure is formed in the formation process of the array common source of the three-dimensional memory.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory, a preparation method thereof, and a photolithography mask. Background technique [0002] Memory is a memory device used to save information in modern information technology. With the increasing demand for integration and data storage density of various electronic devices, it is increasingly difficult for ordinary two-dimensional memory devices to meet the requirements. In this case, three-dimensional (3D) memory emerges as the times require. [0003] In the preparation of three-dimensional memory, the stack structure is mainly formed on the substrate, and the stack structure is divided into several memory cell areas arranged at intervals along the substrate plane direction, thereby forming a memory array; a stepped area is formed around the memory cell area (Stair Steps area, SS area), so that each layer of gate in the memory cell area is condu...

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Problems solved by technology

[0004] However, the current manufacturing process of three-dimensional memory is plagued by local stress, because the memory cell area is surrounded by a filling material layer; and due to process reasons, the filling material layer is easily deformed in the subsequent high-temperature annealing process, thus Squeeze the memory cell area

In addition, since the top pattern of the memory cell area is a large block area (Giant Block, GB), it is often used as an Overlay (OVL) marker in the photolithography process; once the memory cell area boundary is squeezed and deformed, It will directly cause overlay offset and reduce product yield

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