Burr-free asynchronous reset TSPC type D trigger with scanning structure

Abstract

The invention discloses a burr-free asynchronous reset TSPC type D trigger with a scanning structure. The trigger comprises an enable circuit, a first-stage anti-phase logic, a second-stage anti-phaselogic, a third-stage anti-phase logic and a fourth-stage anti-phase logic, the enable circuit outputs an enable signal SE and a reverse signal SEN of the enable signal SE; the first-stage anti-phaselogic outputs a signal ml _ a according to the output of the enable circuit, a scanning signal SI, a data input D, a reset signal R and a clock CP; the second-stage anti-phase logic generates a signalml _ b from the input signal ml _ a under the control of the clock CP, the third-stage anti-phase logic generates a signal s1 _ a from the input signal ml _ b under the control of the clock CP and the reset signal R, and the fourth-stage anti-phase logic inverts the signal s1 _ a to output a signal Q; according to the invention, the burr problem and the power consumption loss can be effectively overcome, the high working speed and the small area are maintained, the general adaptability is improved, and the trigger is suitable for the design of a high-performance microprocessor.

Description

technical field [0001] The invention relates to a high-speed master-slave D flip-flop in the field of high-performance integrated circuit design, in particular to a burr-free asynchronous reset TSPC (True Single Phase Clock, true single-phase clock) type D flip-flop with scanning structure. Background technique [0002] Since the advent of CMOS integrated circuit technology, flip-flops have always been one of the core components of digital integrated circuits. They are the basic units for implementing sequential logic such as pipelines, state machines, counters, and register files. Their speed directly affects the performance of circuits and chips. There are many types of D flip-flops, which are divided into RS flip-flops, JK flip-flops, D flip-flops, T flip-flops and other functional types; according to different circuit structures, they are divided into master-slave structure, sensitive amplifier structure and maintaining blocking structure etc. Among them, the D flip-flo...

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a glitch-free asynchronous reset TSPC type D flip-flop with a scanning structure for the problem of glitches and power consumption in the current traditional TSPC type D flip-flop, and the existin

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