Burr-free asynchronous reset TSPC type D trigger with scanning structure
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- NAT UNIV OF DEFENSE TECH
- Publication Date
- 2020-01-10
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Abstract
Description
technical field
[0001] The invention relates to a high-speed master-slave D flip-flop in the field of high-performance integrated circuit design, in particular to a burr-free asynchronous reset TSPC (True Single Phase Clock, true single-phase clock) type D flip-flop with scanning structure. Background technique
[0002] Since the advent of CMOS integrated circuit technology, flip-flops have always been one of the core components of digital integrated circuits. They are the basic units for implementing sequential logic such as pipelines, state machines, counters, and register files. Their speed directly affects the performance of circuits and chips. There are many types of D flip-flops, which are divided into RS flip-flops, JK flip-flops, D flip-flops, T flip-flops and other functional types; according to different circuit structures, they are divided into master-slave structure, sensitive amplifier structure and maintaining blocking structure etc. Among them, the D flip-flo...