Manufacturing method of redistribution layer, wafer-level packaging method and redistribution layer
A technology for rewiring layers and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid devices, etc., can solve problems such as packaging defects and easy cracking of rewiring layers, so as to improve quality, avoid open circuits, Effect of Yield and Reliability Improvement
Active Publication Date: 2020-02-07
SEMICON MFG INT TIANJIN +1
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[0004] The object of the present invention is to provide a method for manufacturing a rewiring layer, a wafer-level packaging method, and a semiconductor structure, so as to solve the problems in the prior art that the rewiring layer is prone to cracking, causing defects in packaging, etc.
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[0053] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.
[0054] refer to figure 1 , which is a flowchart of a method for manufacturing a redistribution layer provided in this embodiment, the method for manufacturing a redistribution layer includes:
[0055] S1: providing a substrate, on which a first dielectric layer and a plurality of pads located in the first dielectric layer are formed;
[0056]S2: Form a second dielectric layer, the second dielectric layer covers the first dielectric layer, a plurality of multi-hole structures are formed in the second dielectric ...
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The invention provides a manufacturing method of a redistribution layer, a wafer-level packaging method and a semiconductor structure. First, a second dielectric layer is formed on a substrate, then aplurality of multi-through-hole structures exposing a welding pad are formed in the second dielectric layer, afterwards, a redistribution layer is formed, and the redistribution layer covers a part of the second dielectric layer and an inner wall of each through hole in the multi-through-hole structures. Since the plurality of multi-through-hole structures exposing the welding pad are formed in the second dielectric layer, the multi-through-hole structures can reduce stresses of the dielectric layers in the multi-through-hole structures on the redistribution layer, then avoids a redistribution open circuit, improves the packaging quality, and further improves the yield and reliability of a chip.
Description
technical field [0001] The invention relates to the technical field of semiconductor manufacturing technology, in particular to a manufacturing method of a rewiring layer, a wafer-level packaging method and a semiconductor structure. Background technique [0002] Wafer Level Packaging (WLP) is a kind of chip packaging method. After the entire wafer is produced, it is directly packaged and tested on the wafer, and then cut into individual chips. After punching or filling. Wafer-level packaging has the advantages of small package size and excellent electrical performance after packaging, and is easily compatible with wafer manufacturing and chip assembly, which can simplify the process from wafer manufacturing to product shipment and reduce overall production costs. [0003] However, when the wafer-level packaging process is performed, the redistribution layer is prone to cracking, which leads to open circuits of the chip and reduces the yield and reliability of the chip. C...
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IPC IPC(8): H01L21/60H01L23/488
CPCH01L24/13H01L24/02H01L2224/13024H01L2224/02317H01L2224/02331H01L2224/02372H01L2224/02373H01L2224/0239
Inventor 殷原梓
Owner SEMICON MFG INT TIANJIN