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Interface circuit for joint test action group (JTAG) boundary scanning test

A boundary scan test and interface circuit technology, which is applied in the direction of measuring electricity, measuring electrical variables, electronic circuit testing, etc., can solve the problems that other chips cannot perform boundary scan testing, and achieve the effect of level conversion

Active Publication Date: 2020-02-11
LUOYANG INST OF ELECTRO OPTICAL EQUIP OF AVIC
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In order to solve the problem that the signal voltages of multiple boundary scan chips are different or when a certain chip enters a low-voltage sleep mode, other chips cannot perform boundary scan testing, and discloses an interface circuit for JTAG boundary scanning testing

Method used

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  • Interface circuit for joint test action group (JTAG) boundary scanning test
  • Interface circuit for joint test action group (JTAG) boundary scanning test

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specific Embodiment approach

[0018] External 5.0V, 3.3V, 2.5V, 1.8V, 1.5V, 1.2V power supply voltage connections figure 1 Each power selection switch in the DIP switch array circuit shown, each power selection switch matches figure 2 The corresponding interface in the shown CPLD / FPGA signal link selection, data transmission and level matching interface circuit.

[0019] The present invention can match 5V, 3.3V, 2.5V, 1.8V, 1.2V JTAG emulators through the dial switch array; can match 5V, 3.3V, 2.5V, 1.8V, 1.2V JTAG boundary scan chips through the dial switch array , the number of boundary scan chips can be appropriately increased; each boundary scan device is synchronous with TCK (test clock) clock; CPLD / FPGA is used to realize the link selection and data transmission of signals between the JTAG emulator and different voltage chips through programming; The bi-directional level chip and provide suitable power supply voltage can be extended to other voltage emulators and boundary scan devices.

[0020] In...

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Abstract

The invention discloses an interface circuit for joint test action group (JTAG) boundary scanning test and an implementation method. By the interface circuit and the implementation method, the problemthat boundary scanning test cannot be performed when signal voltages of a plurality of boundary scanning chips are different or a certain chip enters a sleep mode is solved. The interface circuit comprises a shift switch array power supply selection circuit and a CPLD / FPGA signal link selection, data transmission and level matching interface circuit. By additionally arranging a CPLD / FPGA and a level conversion chip between a single-voltage JTAG simulator and JTAG boundary chips with different voltages being 5V, 3.3V, 2.5V, 1.8V and 1.2V, simultaneous JTAG boundary scanning test of the boundary scanning chips with different voltages is achieved by the single-voltage JTAG simulator.

Description

technical field [0001] The invention belongs to the technical field of electronic applications and relates to an interface circuit for JTAG boundary scanning test. Background technique [0002] JTAG boundary scan allows serial interconnection boundary scan testing of IEEE 1149.1-compliant integrated circuit ICs, such as microprocessors, DSPs, ASICs, and CPLD / FPGAs, on circuit boards after PCB placement. The JTAG interface is a four-wire Serial (fifth line is optional) access port TAP, including TDI (Test Data In), TDO (Test Data Out), TCK (Test Clock), TMS (Test Mode Select), and TRST (Test Reset ) is optional. [0003] In the current electronic technology application system, the printed circuit board circuit is becoming more and more complex, the number of circuit board layers is increasing, and the electronic devices are highly integrated. The traditional multimeter and oscilloscope test methods can no longer meet the needs. At present, the commonly used method is to app...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2884Y02D10/00
Inventor 张俊刚李号召陈三民王宝星
Owner LUOYANG INST OF ELECTRO OPTICAL EQUIP OF AVIC
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