A three-dimensional stacking method

Abstract

The invention discloses a three-dimensional stacking method, comprising: forming a hydrogen ion implantation layer in a bare silicon chip; depositing a first bonding layer on the front surface of the bare silicon chip; combining the first bonding layer of the bare silicon chip with the Bonding the second bonding layer on the front surface of the carrier sheet with perforations; performing high-temperature splitting on the bare silicon wafer; processing the split interface; performing required processes on the split interface; combining the processed bare silicon wafer with the One device silicon wafer is bonded; the carrier wafer is debonded with wet chemical solution; a stacked structure of two device silicon wafers is formed. The invention integrates the smart-cut slivers technology into the three-dimensional stacking of device silicon wafers, which greatly improves the resource utilization rate of silicon wafers, saves production costs, and avoids grinding belts such as particle contamination, metal contamination, and silicon wafer slivers. The problems that come, improve the stability of the process, and improve the efficiency and yield of production.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a three-dimensional stacking method that does not require back grinding and can recycle and reuse silicon wafers. Background technique [0002] With the development of semiconductor VLSI, the existing technology has approached the physical limit. Driven by the further miniaturization and multi-functionalization of electronic products, other new technologies, new materials, and new technologies have been gradually explored. Three-dimensional stacking technology is one of them. [0003] Three-dimensional stacking technology is to stack multiple silicon wafers through bonding technology to realize a metal interconnection structure on a three-dimensional level, which can reduce interconnection distance, increase transmission speed, reduce device volume, and provide the possibility of heterogeneous structure integration sex. [0004...

AI Technical Summary

Problems solved by technology

However, since the hydrogen ion cleavage requires a very high temperature (generally > 1000 degrees Celsius), it cannot be carried out after bonding with the device wafer (device wafer), and the implantation of hydrogen ions must be completed before the silicon wafer surface device is fabricated, so This method is currently only used to make substrate materials, such as silicon-on-insulator (SOI), which is difficult to use in three-dimensional stacking of device silicon wafers with device layers

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