Universal computing circuit of neural network accelerator

Abstract

The invention discloses a general calculation module circuit of a neural network accelerator. The general calculation module circuit is composed of m universal computing modules PE, any ith universalcomputing module PE is composed of an RAM, 2n multipliers, an adder tree, a cascade adder, a bias adder, a first-in first-out queue and a ReLu activation function module. The single PE convolution configuration, the cascaded PE convolution configuration, the single PE full-connection configuration graph and the cascaded PE full-connection configuration are utilized to respectively construct calculation circuits of different neural networks. According to the invention, the universal computing circuit can be configured according to the variable of the neural network accelerator, so that the neural network can be built or modified more simply, conveniently and quickly, the inference time of the neural network is shortened, and the hardware development time of related deep research is reduced.

Description

technical field [0001] The invention belongs to the field programmable gate array (Field Programmable Gate Array, FPGA) design technical field of an integrated circuit, specifically a general computing module circuit of a neural network accelerator. Background technique [0002] In 2012, AlexNet won the championship of the large-scale visual recognition challenge, and the deep neural network has become a research hotspot again. Among them, the research on the convolutional neural network has received more and more attention, and has been widely used in digital video surveillance and face recognition. , image classification and other fields. The learning process of the convolutional neural network will use a large number of iterative operations and data reading. Because the CPU has a limited number of cores, it cannot make full use of the parallelism existing in the neural network. In order to improve the calculation speed of convolutional neural network, researchers have pr...

AI Technical Summary

Problems solved by technology

[0003] Although the current FPGA platform can realize the development of convolutional neural network, the platform also has limitations:

[0004] 1) When the FPGA platform uses the hardware description language to develop the convolutional neural network, it lacks modular hardware circuit design, cumbersome debugging, and the hardware development cycle of the convolutional neural network is long;

[0005] 2) Since the traditional development method of FPGA is to use the hardware description language to describe the circuit behavior, when designing and building the neural network, it is necessary to consider various variables of the built neural network, such as the size of the convolution kernel, the number of feature maps, and the number of convolutional layers , the number of fully connected layers and network output categories, etc., the hardware design of basic components such as convolutional layers, pooling layers, fully connected layers, and activation function layers is relatively rigid and has poor flexibility. If some variables of the neural network change, it is necessary to Reuse the hardware description language to describe the underlying circuit behavior, which has poor versatility;

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