162 results about "General purpose computation" patented technology

The invention provides a heterogeneous acceleration pooling server system, a pooling resource allocation method and a medium, and relates to the technical field of computers, the heterogeneous acceleration pooling server system comprises a general computing resource pool, an internal bus switching module, an Ethernet switching module and a plurality of heterogeneous computing acceleration resource pools; the internal bus exchange module comprises a plurality of mutually connected high-speed data interconnection modules, each module is provided with a plurality of IO devices, the IO devices of the plurality of high-speed data interconnection modules overall allocate global unique codes, the general computing resource pool configures the required IO devices according to resource requirements after obtaining the resource requirements, and the required IO devices are distributed to the general computing resource pool according to the resource requirements. And establishing a heterogeneous computing resource allocation path to enable the general computing resource pool to be matched with one or more heterogeneous computing acceleration resource pools corresponding to the resource requirements, so that each general computing power unit can access any heterogeneous acceleration device, the system expansion capability is improved, and the resource utilization rate is improved when large-scale and diversified applications are dealt with. And the operation efficiency of the heterogeneous acceleration server is improved.

The invention discloses a neural network extension execution computer system based on RISC-V. The neural network extension execution computer system comprises an RISC-V processor based on an out-of-order execution system structure, a neural network hardware accelerator, an instruction memory, a data memory and a dynamic scheduler. The dynamic scheduler is used for switching different working modes for the computer system according to the current calculation load, and distributing a calculation task to be executed to the RISC-V processor or the neural network hardware accelerator for execution; the working modes comprise a standard calculation mode, a neural network acceleration mode and a low power consumption mode; the computing tasks comprise a general computing task and a neural network computing task. According to the technical scheme, the intelligence of the computer system is improved, and the calculation efficiency, the resource consumption and the power consumption are well balanced.

The invention discloses an optimization method for a multi-head attention mechanism operator oriented to a domestic heterogeneous processor, which improves the efficiency of the multi-head attention mechanism operator from four aspects, and comprises the following steps of: firstly, combining the general computing power of a CPU (Central Processing Unit) and the advantages of a DSP (Digital Signal Processor) in the aspect of parallel computing; a high-performance multi-head attention mechanism operator operation method on a CPU + DSP heterogeneous processor is constructed; secondly, a previous softmax optimization algorithm is used for fusing the two batch processing matrix multiplication and a softmax operator, so that the memory access overhead of DSP equipment is reduced; then, a vector operation instruction of a DSP calculation core is used in the calculation process of a multi-head attention operator, and SIMD calculation characteristics of DSP equipment are fully utilized; and finally, during data transmission and calculation, a double-flow water mechanism is adopted, the data transmission time is covered, and the multi-head attention mechanism operator calculation efficiency is improved.

A system and method for real-time or near real-time multilingual language transformation in telecommunications environments using distributed artificial intelligence (Al). The system includes at least one processor configured to instantiate a plurality of Al agents, each corresponding to a user in a communication session, and to manage their operation via an Al-agent runtime adapter comprising a microkernel agent manager and a virtual machine layer. A language model abstraction layer enables access to language models and Al algorithm libraries through publish-subscribe interfaces. The system supports contextual transformation of speech based on user profile data such as sentiment, emotional tone, and cultural background. Execution can occur on telecommunication-class switches, edge devices, or general-purpose computing hardware. Al agents operate asynchronously, access shared or private memory, and produce personalized, bidirectional linguistic output. The architecture supports secure, scalable deployment across heterogeneous devices and networks.

The invention relates to the field of edge computing and Internet of Things, and discloses a miniature data transaction device which comprises an edge computing unit used for executing a centralized or decentralized matchmaking algorithm and a transaction protocol; the multi-dimensional detection module comprises a compliance detection unit, a safety detection unit, a quality evaluation unit and a scene applicability evaluation unit; the hardware accelerator is used for accelerating a detection task and encryption operation; the communication module supports multi-protocol data transmission; the storage unit is used for caching transaction data and intelligent contract codes; the power management unit is used for controlling the total power consumption of the equipment, and the edge computing unit comprises a hierarchical trusted execution environment architecture consisting of a safe enclave and a general computing unit. According to the method, a hardware isolation architecture of the secure enclave and the general computing unit is adopted, and the dynamic key encryption shared memory technology is combined, so that the effects of privacy computing and efficient matching parallel execution are achieved.

Memory has been playing a major role in the performance, scalability and applicability of General Compute systems, and more recently, in realizing Generative Artificial Intelligence (GenAI) and High-Performance Computing (HPC) systems that scale to thousands of GPUs, CPUs and special-purpose Accelerators. Embodiments herein disclose efficient software-defined protocol terminations and protocol translations utilizing Compute Express Link (CXL), including translations between CXL.mem and CXL.cache protocols. Also disclosed are CXL-based systems, Resource Provisioning Units (RPUs), and Memory Fabric Switches enabling dynamic memory pooling and sharing, host-to-host communication utilizing CXL.mem, CXL.cache and CXL.io, intent-based protocol translations, and optionally seamless interactions between CXL, UALink, NVLink, and / or Ethernet protocols, utilizing a broad range of semantics including IO, Cache, and Memory, optimizing memory access and reducing latency. Some embodiments also enable scalability, flexibility and security in high-performance architectures suited for data centers and next-generation computing environments.

Memory has been playing a major role in the performance, scalability and applicability of General Compute systems, and more recently, in realizing Generative Artificial Intelligence (GenAI) and High-Performance Computing (HPC) systems that scale to thousands of GPUs, CPUs and special-purpose Accelerators. Embodiments herein disclose efficient software-defined protocol terminations and protocol translations utilizing Compute Express Link (CXL), including translations between CXL.mem and CXL.cache protocols. Also disclosed are CXL-based systems, Resource Provisioning Units (RPUs), and Memory Fabric Switches enabling dynamic memory pooling and sharing, host-to-host communication utilizing CXL.mem, CXL.cache and CXL.io, intent-based protocol translations, and optionally seamless interactions between CXL, UALink, NVLink, and / or Ethernet protocols, utilizing a broad range of semantics including IO, Cache, and Memory, optimizing memory access and reducing latency. Some embodiments also enable scalability, flexibility and security in high-performance architectures suited for data centers and next-generation computing environments.

The invention provides an artificial intelligence chip and an operation method thereof. The artificial intelligence chip comprises a tensor core, a tensor transmitting unit, a general computing core, a general transmitting unit and a thread block segmentation unit. In response to operation of the thread block segmentation unit in the first operation mode, the thread block segmentation unit distributes a thread bundle to the general-purpose transmission unit, and the general-purpose transmission unit transmits an instruction to the tensor core and the general-purpose computing core. In response to operation of the thread block segmentation unit in the second operation mode, the thread block segmentation unit distributes a tensor thread bundle involving tensor calculation to the tensor transmitting unit, the tensor transmitting unit transmits a tensor calculation instruction to the tensor core, the thread block segmentation unit distributes a non-tensor thread bundle not involving tensor calculation to the general transmitting unit, and the general transmitting unit transmits a non-tensor thread bundle involving tensor calculation to the general transmitting unit. And the general transmitting unit transmits the non-tensor calculation instruction to the general calculation core.

Provided in the embodiments of the present application are a server system, a resource scheduling method for a server system, and a chip and a chiplet. The server system comprises: a multivariate computing resource pool, a data storage resource pool, a switching module and a control module, wherein the multivariate computing resource pool comprises a general computing resource pool and a heterogeneous computing resource pool, the general computing resource pool comprising a group of general computing units, and the heterogeneous computing resource pool comprising a group of heterogeneous computing units, and the multivariate computing resource pool is connected to the data storage resource pool via the switching module by means of a cache consistency bus inside the server system; the data storage resource pool comprises data storage resources allowed to be shared by multivariate computing resources in the multivariate computing resource pool; and the control module is configured to perform computing power scheduling on the multivariate computing resources in the multivariate computing resource pool, and dynamically allocate the data storage resources in the data storage resource pool to the multivariate computing resources in the multivariate computing resource pool.

The present invention relates to the technical field of wireless communications, and provides a processor, a chip, a network device and a wireless communication data processing method wherein the processor comprises: at least one general purpose computing core configured to execute a general purpose computing task; at least one tensor calculation core configured to perform a matrix multiplication task; at least one wireless communication computing core configured to execute a preset wireless communication computing task; the general computing core, the tensor computing core and the wireless communication computing core are all in communication connection with the shared memory, and the shared memory is configured to be used for data transmission among the computing cores. Various special computing cores are integrated on the processor, a shared memory architecture is adopted, efficient on-chip data interaction between a communication computing task and an AI computing task is achieved, and the method has the advantages of being low in delay, high in bandwidth and high in integration level.

Disclosed are a method and a platform for computational optimization of machine learning. The method includes: partitioning, through a partitioned edge, a machine learning computation graph into a data worker subgraph constituted by upstream nodes of stateful nodes and a training worker subgraph constituted by the stateful nodes and downstream nodes of the stateful nodes; and on each side of the partitioned edge, adding a data sending node to the data worker subgraph and adding a data receiving node to the training worker subgraph, respectively. By dividing the computation graph on the basis of whether a node is stateful or stateless and inserting communication nodes, a data worker and a training worker in a same task can be decoupled, so that general-purpose computational resources involved in the data worker at runtime can be dynamically allocated. Furthermore, through combining with a scheduler, the general-purpose computational resources can be scheduled across clusters.

The invention provides a thread block scheduling module, a general-purpose computing graphic processing unit, equipment and a product, and relates to the technical field of data process.The method comprises the steps that an operation data analysis unit conducts data analysis on all first thread blocks of a computing task issued by a host, and second thread blocks sharing data with all the first thread blocks are determined; the mapping relation between the first thread block and the second thread block is written into a thread block data mapping table of the queue management unit; the resource management unit is used for recording available resources and used resources of each streaming multiprocessor and information of a thread block currently allocated to each streaming multiprocessor; and the thread block allocation unit is used for allocating the thread blocks of the first target thread block to the corresponding stream multiprocessors according to the thread block data mapping table of the first target thread block under the condition of detecting that any stream multiprocessor recorded by the resource management unit has idle available resources.

The invention discloses an intelligent collaborative scheduling system and method for a general computing and intelligent computing fusion scene, and relates to the technical field of computing power resource management and scheduling. In order to solve the problem that isomerous computing power resource islands are difficult to collaborate, the system comprises a computing power access layer used for executing specified operation on isomerous computing power resources through a standardized access template, abstracting the isomerous computing power resources into a unified logic computing power unit and registering the unified logic computing power unit into a computing power pool; the resource management layer is used for continuously monitoring and collecting static attributes and dynamic states of computing power resources to form a global resource real-time view; the business processing layer is used for receiving the business submitted by the user, analyzing and identifying the business demand, converting the business demand into a demand vector, and generating a dynamic arrangement scheme based on the real-time view and the multi-target strategy library; and the collaborative scheduling execution layer is used for converting the dynamic arrangement scheme into an instruction adaptive to various APIs and completing computing power resource allocation and service starting. According to the invention, unified management and intelligent cooperative scheduling of computing power resources can be realized.

Techniques are presented for a computer-implemented method that may be implemented using a blockchain network. The computer-implemented method includes: monitoring a system to detect a challenge to a proposer string in response to a request, and as a result of detecting the challenge: placing a first digital asset and a second digital asset under exclusive control of a group of nodes via a public key associated with a group of nodes, wherein the first and second digital assets are configured to be released when a threshold number of members of the group of nodes generate a valid signature for the public key associated with the group of nodes; resolving the challenge using a blockchain network; and distributing, by the group of nodes, digital assets from the first digital asset and the second digital asset to one or more parties of the system based at least in part on the solution.

A differential matching prefetcher for coping with irregular memory access includes: an access index table, an access target table, a differential matching module, an index queue, an indirect memory access candidate scoreboard, an address generator, an indirect memory access relationship table, a prefetch status handling register, a repetition filter, a continuous address filter, and a range prefetch table. The differential matching prefetcher is configured to monitor events of access requests and data responses between a computing core and a first level of cache, as well as between the first level of cache and a second level of cache. The differential matching prefetcher may be applied in various general-purpose computing architectures adopting a hierarchical storage design to realize mode capture and data prefetch for irregular indirect memory access, reduce long-delay storage access overhead caused by the irregular memory access, and increase instructions per cycle (IPC) of the computing architectures.

The invention provides a matrix multiplication pipeline calculation method and device, an AI chip, electronic equipment, a medium and a program product, and relates to the field of artificial intelligence, in particular to the field of chips. According to the specific implementation scheme, in response to a matrix multiplication request, a plurality of general calculation components and a plurality of special calculation components in a chip are triggered in parallel, and in each conversion round, the general calculation components obtain matrix element types required by conversion from a first matrix and a second matrix and identify a conversion completion state; and under each calculation round, when the special calculation part queries that each conversion matrix element needing to be calculated in the current calculation round is converted, each conversion matrix element is acquired from the matched general calculation part to execute matrix multiplication calculation. The general calculation part and the special calculation part are executed in parallel, so that the time consumption of data type conversion and the time consumption of matrix multiplication can be mutually masked, the performance of the special calculation part is fully exerted, and the efficiency of matrix multiplication calculation and the performance of an AI chip are improved.

The invention discloses a method for effectively simulating general quantum computing based on a classical circuit network, and relates to the technical field of quantum computing simulation, and the method comprises the following specific steps: converting data into a voltage signal through input voltage coding, constructing a single-bit gate and a two-bit gate by using an operational amplifier and an analog multiplier, and constructing a single-bit gate and a two-bit gate; according to the invention, the general quantum computation is simulated by a classical circuit network, an n-bit unitary matrix is decomposed and reconstructed by means of input voltage coding quantum state and voucher / two-bit gate modular design, and the high-efficiency simulation of general quantum computation is realized. Quantum gate linear transformation is reproduced, quantum calculation universality is achieved, voltage signals and data are converted through a reflection formula, signal distortion is avoided, multi-level gate circuit cascading is supported, and a flexible and stable platform is provided for quantum algorithm verification and the like.

The invention discloses a device and a method for deploying DeepSeek. The device comprises a Weixin H8000 processor, a SW A1 accelerator card, an AI third-party library, an acceleration library, basic software, a compiler, a compiling framework and a DeepSeek large model. The Weixin H8000 processor serves as a core computing unit and is responsible for general computing and resource scheduling; the SW A1 acceleration card provides AI special computing power acceleration; the AI third-party library and the acceleration library optimize the algorithm execution efficiency; the basic software manages system resources; the compiler and the compiling framework are used for adapting software codes to domestic hardware; the DeepSeek large model serves as a top layer AI application, and all component resources of a bottom layer are called; the Weixin H8000 processor and the Shenwei A1 accelerator card construct a heterogeneous computing resource pool to integrate computing power, basic software performs unified scheduling, an AI acceleration library and a compilation framework optimize algorithm execution efficiency, an RDMA high-speed network improves data interaction performance, and a DeepSeek large model cooperatively calls computing power resources of all components to complete an AI computing task. The problem that networked artificial intelligence products lack privacy protection is solved.

The embodiment of the invention provides a photoelectric Transform accelerator cooperation method and device, and aims to efficiently process Transform model calculation. Firstly, according to the size M of an optical chip static random access memory on an optical computing chip and feature dimensions d of a query matrix Q, a key matrix K and a value matrix V, Q is divided into Tr sub-blocks, and K and V are respectively divided into Tc sub-blocks. Then, the universal computing chip and the optical computing chip are in interactive communication, the jth sub-block of K and V is transmitted to the optical computing chip firstly, and then the ith sub-block of Q is transmitted circularly for the sub-block. The optical computing chip computes a local attention score matrix Sij and then transmits the matrix back, the general computing chip carries out nonlinear processing on the matrix to obtain a local attention weight matrix Pij, the maximum value mij of each row of the Sij and the sum lij of each row of the Pij are computed, and m, l and O are updated until all sub-blocks K and V are processed. According to the method, through photoelectric collaboration and block calculation, resource utilization is optimized, and calculation efficiency is improved.

The invention discloses a device and a method for realizing a register block shared by a general-purpose computing core and a tensor core, a tensor core read request unit sends a read request and stores the read request in a tensor core read request queue, and a life cycle counter and a clock cycle counter are triggered to start counting; the life cycle counter records life cycle values of read requests in the tensor core read request queue; the tensor core read request scheduler transmits a to-be-executed read request to the register block when the life cycle value of the to-be-executed read request reaches a preset value, so as to read a tensor core operand from the register block and store the tensor core operand in a tensor core operand cache; the priority of the general calculation core is higher than that of the tensor core before the life cycle value of the to-be-executed read request reaches a preset value; the clock period counter triggers the tensor core operand cache to send the tensor core operand to the tensor core execution unit when the count value reaches a preset trigger value. According to the invention, the read bandwidth of the register block can be utilized to the maximum extent, and the overall performance is effectively improved.

The invention discloses a method for improving data acquisition / writing stability, and relates to the technical field of industrial control systems. The method comprises the following steps: firstly, deploying a real-time operating system kernel on general computing hardware, and carrying out real-time transformation on a hardware interface driving program of the real-time operating system kernel so as to lay a deterministic response foundation; secondly, real-time adaptation is carried out on an engine when the container runs, so that the engine has the capability of calling a kernel real-time interface; meanwhile, a non-real-time data acquisition / write-in program is packaged in a standard container mirror image. And finally, through the adapted container runtime engine, creating and running the container instances on the real-time kernel, thereby ensuring the deterministic execution of key real-time tasks on a unified hardware platform, and flexibly deploying non-real-time tasks through a containerization technology to achieve the comprehensive target of efficient utilization of resources and performance isolation.

The invention provides a general purpose computing unit and computing equipment. The general-purpose computing unit comprises a plurality of execution units, wherein each execution unit is used for executing an operation instruction by taking a thread bundle as a unit; and a thread local register for each execution unit, including a plurality of thread beam registers allocated for a plurality of thread beams run by the execution unit, the plurality of thread beam registers being non-overlapping, where the thread local register further includes a shared register shared by the plurality of thread beams.

The invention belongs to the technical field of computers, and particularly relates to a dynamically configured cockpit host video test multiplexing method. The method aims at solving the problems that a traditional testing means is poor in universality, incomplete in coverage and low in automation degree. A structural equipment description file is constructed by analyzing a host technical document, an adaptive dynamic test configuration template is automatically generated in combination with a test case library, and flexible configuration of multi-channel video stream parameters, abnormal injection modes and time sequence logic is supported. A containerized virtual signal source is deployed on a universal computing platform, and an analog video stream conforming to an input specification is generated in real time. Through the equipment description driving and virtualization signal generation technology, the multiplexing capability and coverage integrity of the testing system are improved, efficient and automatic testing of multiple types of hosts is achieved, and the hardware cost and the deployment period are remarkably reduced.

The invention provides a general purpose computing unit and an instruction scheduling method for the general purpose computing unit. The general-purpose computing unit comprises a plurality of execution units, wherein each execution unit is used for executing an operation instruction by taking a thread bundle as a unit; and an instruction scheduler for determining a priority of the plurality of operation instructions based on whether the multiplexing flag exists, and scheduling each operation instruction to one of the plurality of execution units based on the priority; wherein each execution unit comprises one or more reuse registers, each reuse register is used for registering an operand of a previous operation instruction and a label, and the label is used for indicating an address and a thread bundle of the operand; and the instruction decoding unit is used for decoding the received operation instruction to determine the reading position of the operand of the operation instruction. The instruction is preferentially scheduled by adding a reuse mark to the whole operation instruction, so that the hit rate of the operand is improved, and excessive instruction bit fields do not need to be occupied.

The invention discloses a high-availability distributed memory pool system based on erasure codes and a method thereof, which are designed for coping with errors such as node faults and page loss, are suitable for general computing scenes deployed on a large scale, and ensure high availability of applications such as big data machine learning, and the method does not need kernel mode code modification, and runs in a user mode through a computing node (QEMU). Physical and remote memories are managed in a unified manner, and memory management of a cache line level is realized. A memory page is divided into K data blocks and P verification blocks by using an erasure code technology, and the K data blocks and the P verification blocks are stored in different remote memory nodes in a scattered manner. In order to reduce the influence of erasure codes on the read-write performance of the memory, a background backup mechanism based on monitoring is introduced: a memory monitor periodically scans a memory page and verifies a node state, reports a fault to a computing node once the fault is found, and triggers a fault processing flow. And the stability and the reliability of the distributed memory system are effectively improved.

The embodiment of the invention discloses a task execution method and system. The method comprises the following steps: in response to a to-be-executed artificial intelligence task, identifying task features of the artificial intelligence task, and obtaining a first resource portrait of a general computing domain and a second resource portrait of an intelligent computing domain in a hybrid cloud environment; determining a first matching degree between the task feature and the first resource portrait, and determining a second matching degree between the task feature and the second resource portrait; and according to a numerical relationship between the first matching degree and the second matching degree, determining a target computing domain from the general computing domain and the intelligent computing domain, and allocating the artificial intelligence task to the target computing domain, so that the target computing domain is utilized to execute the artificial intelligence task. According to the technical scheme provided by the embodiment of the invention, the optimal balance between the cost and the performance can be realized.

The invention provides a data migration method and device based on a computing pipeline, a processor and a related product. The data migration method based on the calculation pipeline comprises the following steps: receiving a data migration instruction of to-be-processed data; the data migration instruction is used for indicating a target data migration operation on the to-be-processed data; determining a target complexity classification corresponding to the target data migration operation based on a corresponding relationship between a preset data migration operation and the complexity classification; if the target complexity is classified as a preset complex operation type, converting the to-be-processed data and the data migration instruction into a general calculation task; the preset complex operation type comprises data conversion and data analysis in the data migration operation; and executing the general-purpose computing task through the general-purpose computing pipeline to obtain target data after the target data migration operation is completed. According to the method, the hardware and software complexity of the graphics processor for realizing data migration can be reduced.

The application discloses a reconfigurable processor and an execution method fusing neuromorphic and general computing, and comprises a total control module and an on-chip network module, wherein the on-chip network module comprises a control module, a pulse storage module, a weight storage module, a pulse time module, a LIF neuron module and a classification comparison module. The execution method comprises the following steps: acquiring an input data set; selecting a working mode of the on-chip network module according to the input data set; and performing data recognition processing on the input data set according to the working mode, and outputting a data recognition output result. The application realizes the working of a central processing unit (CPU) and a spiking neural network (SNN) in a single core, thereby improving the utilization rate of a heterogeneous core and reducing the delay of core-to-accelerator communication. The application can be widely applied to the technical field of neural network accelerator as a reconfigurable processor and an execution method fusing neuromorphic and general computing.

The invention discloses a data processing device and a data processing method, and relates to the technical field of data processing.The device comprises a processor, a memory unit and an input and output interface, the processor comprises a kernel, a memory management unit, a register, a first-level cache unit and a second-level cache unit, and the device further comprises a cache division control module, a first-level cache division module and a second-level cache division module, the determining module is used for determining a second target cache block in the first-level cache unit corresponding to the security computing program and a first target cache block in the second-level cache unit when the general computing program and the security computing program are executed in parallel; the memory division control module is used for determining a target memory block corresponding to the security calculation program; the input and output interface division control module is used for determining a target input and output interface corresponding to the security calculation program; wherein the register comprises a first register corresponding to the general-purpose computing program and a second register corresponding to the security computing program, so that the kernel runs the general-purpose computing program and the security computing program in parallel.

A processor executes an instruction to perform a comparison between a source value and a value stored in memory at a specified address. If the comparison passes, the processor writes the source value to memory at the specified address and writes a payload to a payload destination address in an atomic operation. The instruction includes an opcode indicating the comparison and fields specifying the source value, addresses, and payload. The payload may have arbitrary length. A Test-And-Update (TAU) operation associates the payload with the atomic operation while maintaining native bit-width for the comparison. This enables efficient handling of larger payloads without compromising performance of existing comparison logic, providing enhanced functionality for graphics and general-purpose computing applications.