75 results about "General purpose computation" patented technology

A system and method for real-time or near real-time multilingual language transformation in telecommunications environments using distributed artificial intelligence (Al). The system includes at least one processor configured to instantiate a plurality of Al agents, each corresponding to a user in a communication session, and to manage their operation via an Al-agent runtime adapter comprising a microkernel agent manager and a virtual machine layer. A language model abstraction layer enables access to language models and Al algorithm libraries through publish-subscribe interfaces. The system supports contextual transformation of speech based on user profile data such as sentiment, emotional tone, and cultural background. Execution can occur on telecommunication-class switches, edge devices, or general-purpose computing hardware. Al agents operate asynchronously, access shared or private memory, and produce personalized, bidirectional linguistic output. The architecture supports secure, scalable deployment across heterogeneous devices and networks.

The present invention relates to the technical field of wireless communications, and provides a processor, a chip, a network device and a wireless communication data processing method wherein the processor comprises: at least one general purpose computing core configured to execute a general purpose computing task; at least one tensor calculation core configured to perform a matrix multiplication task; at least one wireless communication computing core configured to execute a preset wireless communication computing task; the general computing core, the tensor computing core and the wireless communication computing core are all in communication connection with the shared memory, and the shared memory is configured to be used for data transmission among the computing cores. Various special computing cores are integrated on the processor, a shared memory architecture is adopted, efficient on-chip data interaction between a communication computing task and an AI computing task is achieved, and the method has the advantages of being low in delay, high in bandwidth and high in integration level.

The invention discloses an intelligent collaborative scheduling system and method for a general computing and intelligent computing fusion scene, and relates to the technical field of computing power resource management and scheduling. In order to solve the problem that isomerous computing power resource islands are difficult to collaborate, the system comprises a computing power access layer used for executing specified operation on isomerous computing power resources through a standardized access template, abstracting the isomerous computing power resources into a unified logic computing power unit and registering the unified logic computing power unit into a computing power pool; the resource management layer is used for continuously monitoring and collecting static attributes and dynamic states of computing power resources to form a global resource real-time view; the business processing layer is used for receiving the business submitted by the user, analyzing and identifying the business demand, converting the business demand into a demand vector, and generating a dynamic arrangement scheme based on the real-time view and the multi-target strategy library; and the collaborative scheduling execution layer is used for converting the dynamic arrangement scheme into an instruction adaptive to various APIs and completing computing power resource allocation and service starting. According to the invention, unified management and intelligent cooperative scheduling of computing power resources can be realized.

The invention discloses a method for effectively simulating general quantum computing based on a classical circuit network, and relates to the technical field of quantum computing simulation, and the method comprises the following specific steps: converting data into a voltage signal through input voltage coding, constructing a single-bit gate and a two-bit gate by using an operational amplifier and an analog multiplier, and constructing a single-bit gate and a two-bit gate; according to the invention, the general quantum computation is simulated by a classical circuit network, an n-bit unitary matrix is decomposed and reconstructed by means of input voltage coding quantum state and voucher / two-bit gate modular design, and the high-efficiency simulation of general quantum computation is realized. Quantum gate linear transformation is reproduced, quantum calculation universality is achieved, voltage signals and data are converted through a reflection formula, signal distortion is avoided, multi-level gate circuit cascading is supported, and a flexible and stable platform is provided for quantum algorithm verification and the like.

The invention discloses a method for improving data acquisition / writing stability, and relates to the technical field of industrial control systems. The method comprises the following steps: firstly, deploying a real-time operating system kernel on general computing hardware, and carrying out real-time transformation on a hardware interface driving program of the real-time operating system kernel so as to lay a deterministic response foundation; secondly, real-time adaptation is carried out on an engine when the container runs, so that the engine has the capability of calling a kernel real-time interface; meanwhile, a non-real-time data acquisition / write-in program is packaged in a standard container mirror image. And finally, through the adapted container runtime engine, creating and running the container instances on the real-time kernel, thereby ensuring the deterministic execution of key real-time tasks on a unified hardware platform, and flexibly deploying non-real-time tasks through a containerization technology to achieve the comprehensive target of efficient utilization of resources and performance isolation.

The invention provides a general purpose computing unit and computing equipment. The general-purpose computing unit comprises a plurality of execution units, wherein each execution unit is used for executing an operation instruction by taking a thread bundle as a unit; and a thread local register for each execution unit, including a plurality of thread beam registers allocated for a plurality of thread beams run by the execution unit, the plurality of thread beam registers being non-overlapping, where the thread local register further includes a shared register shared by the plurality of thread beams.

The invention belongs to the technical field of computers, and particularly relates to a dynamically configured cockpit host video test multiplexing method. The method aims at solving the problems that a traditional testing means is poor in universality, incomplete in coverage and low in automation degree. A structural equipment description file is constructed by analyzing a host technical document, an adaptive dynamic test configuration template is automatically generated in combination with a test case library, and flexible configuration of multi-channel video stream parameters, abnormal injection modes and time sequence logic is supported. A containerized virtual signal source is deployed on a universal computing platform, and an analog video stream conforming to an input specification is generated in real time. Through the equipment description driving and virtualization signal generation technology, the multiplexing capability and coverage integrity of the testing system are improved, efficient and automatic testing of multiple types of hosts is achieved, and the hardware cost and the deployment period are remarkably reduced.

The invention provides a general purpose computing unit and an instruction scheduling method for the general purpose computing unit. The general-purpose computing unit comprises a plurality of execution units, wherein each execution unit is used for executing an operation instruction by taking a thread bundle as a unit; and an instruction scheduler for determining a priority of the plurality of operation instructions based on whether the multiplexing flag exists, and scheduling each operation instruction to one of the plurality of execution units based on the priority; wherein each execution unit comprises one or more reuse registers, each reuse register is used for registering an operand of a previous operation instruction and a label, and the label is used for indicating an address and a thread bundle of the operand; and the instruction decoding unit is used for decoding the received operation instruction to determine the reading position of the operand of the operation instruction. The instruction is preferentially scheduled by adding a reuse mark to the whole operation instruction, so that the hit rate of the operand is improved, and excessive instruction bit fields do not need to be occupied.

The embodiment of the invention discloses a task execution method and system. The method comprises the following steps: in response to a to-be-executed artificial intelligence task, identifying task features of the artificial intelligence task, and obtaining a first resource portrait of a general computing domain and a second resource portrait of an intelligent computing domain in a hybrid cloud environment; determining a first matching degree between the task feature and the first resource portrait, and determining a second matching degree between the task feature and the second resource portrait; and according to a numerical relationship between the first matching degree and the second matching degree, determining a target computing domain from the general computing domain and the intelligent computing domain, and allocating the artificial intelligence task to the target computing domain, so that the target computing domain is utilized to execute the artificial intelligence task. According to the technical scheme provided by the embodiment of the invention, the optimal balance between the cost and the performance can be realized.

The invention provides a data migration method and device based on a computing pipeline, a processor and a related product. The data migration method based on the calculation pipeline comprises the following steps: receiving a data migration instruction of to-be-processed data; the data migration instruction is used for indicating a target data migration operation on the to-be-processed data; determining a target complexity classification corresponding to the target data migration operation based on a corresponding relationship between a preset data migration operation and the complexity classification; if the target complexity is classified as a preset complex operation type, converting the to-be-processed data and the data migration instruction into a general calculation task; the preset complex operation type comprises data conversion and data analysis in the data migration operation; and executing the general-purpose computing task through the general-purpose computing pipeline to obtain target data after the target data migration operation is completed. According to the method, the hardware and software complexity of the graphics processor for realizing data migration can be reduced.

The application discloses a reconfigurable processor and an execution method fusing neuromorphic and general computing, and comprises a total control module and an on-chip network module, wherein the on-chip network module comprises a control module, a pulse storage module, a weight storage module, a pulse time module, a LIF neuron module and a classification comparison module. The execution method comprises the following steps: acquiring an input data set; selecting a working mode of the on-chip network module according to the input data set; and performing data recognition processing on the input data set according to the working mode, and outputting a data recognition output result. The application realizes the working of a central processing unit (CPU) and a spiking neural network (SNN) in a single core, thereby improving the utilization rate of a heterogeneous core and reducing the delay of core-to-accelerator communication. The application can be widely applied to the technical field of neural network accelerator as a reconfigurable processor and an execution method fusing neuromorphic and general computing.

A processor executes an instruction to perform a comparison between a source value and a value stored in memory at a specified address. If the comparison passes, the processor writes the source value to memory at the specified address and writes a payload to a payload destination address in an atomic operation. The instruction includes an opcode indicating the comparison and fields specifying the source value, addresses, and payload. The payload may have arbitrary length. A Test-And-Update (TAU) operation associates the payload with the atomic operation while maintaining native bit-width for the comparison. This enables efficient handling of larger payloads without compromising performance of existing comparison logic, providing enhanced functionality for graphics and general-purpose computing applications.

The invention relates to a multi-expansibility intelligent service unit based on an S5000C + 310P architecture, and belongs to the technical field of computers. The intelligent service unit comprises a VPX case, an S5000C general-purpose computing module, a 310P intelligent module, a network switching module, a power module, a timing system module and a bus bottom plate, wherein the S5000C general-purpose computing module and the 310P intelligent module are interconnected through PCIe (Peripheral Component Interconnect Express). According to the method, the S5000C general computing power and the 310P AI computing power are fused, so that multi-task parallel processing is realized, the data operation and AI reasoning efficiency is remarkably improved, the processing delay is reduced, and the intensive computing scene requirements are met; through the modular integrated design, disassembly, assembly, debugging and later expansion and upgrade are facilitated, the operation and maintenance workload and cost are reduced, and the deployment flexibility is improved.

The embodiment of the invention provides an intelligent control method for an aero-engine and related equipment, and belongs to the technical field of data processing. The method comprises the steps that if it is determined that the type of a calculation task is a general calculation task, a central processing unit is scheduled to execute processing of to-be-processed data; if it is determined that the calculation task type is the intelligent calculation task, a neural network processor unit is scheduled to execute processing of the to-be-processed data; if it is determined that the calculation task type is a digital signal processing task, a digital signal processor platform is scheduled to execute processing of the to-be-processed data; when the neural network processor units are scheduled to execute the intelligent computing task, if it is detected that the computing power of the neural network processor unit of the main platform is insufficient, part of the to-be-processed data or the computing sub-graph is distributed to the neural network processor unit of at least one auxiliary platform for parallel processing. According to the embodiment of the invention, the real-time and reliability requirements of a complex intelligent processing task can be met in a computing environment of an aero-engine.

A process plant and industrial control system architecture includes a generalized compute fabric that is agnostic or indifferent to the physical location at which the compute fabric is implemented, includes one or more physical control or field devices located at one or more specific sites at which a product or process is being manufactured and further includes a transport network that securely provides communications between the compute fabric and the pool of physical devices. The compute fabric includes an application layer that includes configured containers or containerized software modules that perform various control, monitoring and configuration activities with respect to one or more devices, control strategies and control loops, sites, plants, or facilities at which control is performed, and includes a physical layer including computer processing and data storage equipment that can be located at any desired location, including at or near a site, plant, or facility at which control is being performed, at a dedicated location away from the location at which control is being performed, in re-assignable computer equipment provided in the cloud, or any combination thereof. This control architecture enables significant amounts of both computer processing and IT infrastructure that is used to support a process plant, an industrial control facility or other automation facility to be implemented in a shared, in an offsite and / or in a virtualized manner that alleviates many of the communications and security issues present in current process and industrial control systems that attempt to implement control with shared or virtualized computing resources set up according to the well-known Purdue model.The industrial control system architecture is protected via more secure and customizable techniques as compared to those used in Purdue model-based control systems. For example, communications between any (and in some cases, all) endpoints of the system may be protected via one or more virtual private networks to which authenticated endpoints must be authorized to access. Endpoints may include, for example, containerized components, physical components, devices, sites or locations, the compute fabric, and the like, and the VPNs may include mutually-exclusive and / or nested VPNs. External applications and services, whether automated or executing under the purview of a person, may access information and services provided by the system via only APIs, and different sets of APIs may be exposed to different users that have been authenticated and authorized to access respective sets of APIs.A configuration system operates within the compute fabric to enable a user to easily make configuration changes to the compute fabric as the user does not generally need to specify the computer hardware within the compute fabric to use to make the configuration changes, making it possible for the user to deploy new configuration elements with simple programming steps, and in some cases with the push of a button.

A computing device including a plurality of sensors, a system-on-module, a safety microcontroller and a plurality of communication interfaces communicatively coupling the system-on-module, the safety microcontroller and the plurality of sensors together. The system-on module can include an integrated interconnection of a plurality of different types of cores and one or more different types of memory. The system-on module can be configured to control operation and or performance of a system. The safety microcontroller can be configured to provide safety supervision of the system-on-module.

The invention relates to the technical field of power electronic control, and provides a general control platform and method for an SST modular power unit and a readable storage medium. The hardware layer comprises a general computing unit supporting multi-type signal processing, a configurable interface module adapted to different external devices, and a power management unit providing general power supply for hardware; the software layer runs on the hardware layer, and the software layer comprises a hardware abstraction layer used for shielding hardware differences, a control algorithm module dynamically configured to adapt to various SST topologies, and a communication mechanism supporting unified data interaction; the software layer and the hardware layer are cooperatively arranged through the hardware abstraction layer. The problems of long research and development period and high cost are solved, and technology multiplexing and platform sharing of different SST product lines are realized; when topology or parameters change, a control system does not need to be modified or redesigned on a large scale, SST technology iteration is accelerated, and large-scale application is guaranteed.

The application provides a method and system for deploying a large language model on a graphics card with limited computing power, relating to the technical field of software engineering, and aiming at the characteristics of the target graphics card hardware architecture lacking a dedicated matrix acceleration unit, reconstructing key operators required by the large language model, including: adapting the core computing process of the key operator to be executed by the general computing unit of the graphics card; optimizing the key operator to make it suitable for a computing scenario with an input dimension of 1xN; quantizing the model weights in the key operator by 4-bit integers and using 16-bit floating-point numbers for activation in the forward calculation process; constructing a lightweight inference engine; loading the target large language model and executing the inference task on the target graphics card by using the lightweight inference engine. The application realizes system-level improvement in three dimensions of hardware compatibility, resource utilization, and inference efficiency, and provides a feasible technical path for deploying advanced large models on a wide range of existing and low-power graphics cards.

The invention relates to the technical field of data center scheduling, and particularly discloses a data center intelligent scheduling system and method oriented to heterogeneous computing power resources, and the system comprises the steps that a resource sensing module obtains the real-time resource load state of each heterogeneous computing node and a resource gap prediction result in a future preset time period; the queue construction module constructs an AI training task queue and a general calculation task queue; the hierarchical scheduling module dynamically adjusts the resource quota of each heterogeneous computing node to the two types of task queues based on the real-time resource load state of each heterogeneous computing node and a resource gap prediction result in a future preset time period; when the node load of the heterogeneous computing node exceeds a preset load threshold value, the fault self-healing module migrates a container running on the corresponding heterogeneous computing node to a low-load heterogeneous computing node, and adjusts a data storage path of the migrated container based on a multi-path optimization strategy of the distributed storage system; and the operation efficiency and the service quality of the data center are comprehensively improved.

The invention discloses an AI accelerator card information detection and emergency response method based on an agent chip, and relates to the technical field of information security, and the method comprises the following steps: when an Agent chip is in a starting state, periodically executing the following operations: collecting multi-dimensional end side operation data, when the network environment meets the uploading condition, the data is uploaded to a cloud server for remote decision making, and attack recognition and instruction issuing are achieved; when the network environment does not meet the uploading condition, the chip locally executes self-decision and implements preliminary protection, so that protection failure caused by network disconnection or too high time delay is avoided; through combination of cloud decision and end-side local self-decision, high reliability of protection under a normal network is guaranteed, safety under a weak network or no network environment is achieved, meanwhile, a chip is deployed by means of a general computing unit, core computing resources of the accelerator card do not need to be occupied, and the cost is reduced on the premise that efficient operation of the AI accelerator card is guaranteed. And the real-time performance, continuity and environmental adaptability of information detection are comprehensively improved.

The application discloses a general calculation method for tunnel engineering quantity, which is suitable for general program calculation of inner contour of various tunnels and engineering quantity of tunnel structure, and can calculate the inner contour area of tunnels with different section forms such as single circle, three-circle and five-circle under the condition of being free from various software platforms and being free from human control.

The application discloses a general-purpose computer hologram generation method and system based on structured propagation, equipment, medium and product, and relates to the field of computer holography. The method comprises the following steps: decoupling a zero-frequency reference diagonal spectrum method transfer function to construct a structured propagation model; obtaining a target scene graph and a laser wavelength; based on the target scene graph and the laser wavelength, a structured propagation model is used to obtain a structure normalized input field; the structure normalized input field is input into a hologram generation model to obtain a pure phase hologram; and the hologram generation model is obtained by training a U-net network through a sample input field and a sample pure phase hologram. The application can improve the accuracy of hologram generation.

The application provides an underwater unmanned submarine-based electronic computing method and system, which comprises a case and a plurality of board card modules arranged in the case; the plurality of board card modules are installed in a stacked manner through stacked electrical connectors and comprise at least one general computing module and at least one interface expansion module; wherein the plurality of board card modules realize internal data interaction between the board cards through a high-speed Ethernet; the high-speed Ethernet comprises a control plane network for transmitting control signaling and a data plane network for transmitting large-capacity service data; the transmission rate of the data plane network is higher than that of the control plane network; the general computing module is used for fusing and processing data collected by the interface expansion module to generate control instructions; the interface expansion module is used for connecting with external devices of the underwater unmanned submarine, receiving data of the external devices and outputting the control instructions to the external devices, so that the modularization level and development efficiency of the system are greatly improved.

One embodiment provides circuitry coupled with cache memory and a memory interface, the circuitry to compress compute data at multiple cache line granularity, and a processing resource coupled with the memory interface and the cache memory. The processing resource is configured to perform a general-purpose compute operation on compute data associated with multiple cache lines of the cache memory. The circuitry is configured to compress the compute data before a write of the compute data via the memory interface to the memory bus, in association with a read of the compute data associated with the multiple cache lines via the memory interface, decompress the compute data, and provide the decompressed compute data to the processing resource.

The embodiment of the invention provides a fusion processor and a fusion processing method. The fusion processor comprises a central processing unit front end used for performing instruction fetching, decoding and scheduling on a central processing unit instruction set; the graphics processor front end is used for performing instruction fetching, decoding and scheduling on a graphics processor instruction set; and the shared execution unit is used for being driven by the central processing unit front end to execute the central processing unit instruction in a first time period and driven by the graphics processing unit front end to execute the graphics processing unit instruction set in a second time period, and the first time period is different from the second time period. The embodiment of the invention not only has the processing capability of general calculation, but also has the processor capability of parallel calculation.

The present application relates to the technical field of computers and provides a heterogeneous accelerated pooling server system, a pooling resource allocation method, and a medium. The heterogeneous accelerated pooling server system comprises a general-purpose computing resource pool, an internal bus switching module, an Ethernet switching module, and a plurality of heterogeneous accelerated computing resource pools. The internal bus switching module comprises a plurality of interconnected high-speed data interconnection modules, each module is provided with a plurality of IO devices, and the IO devices of the plurality of high-speed data interconnection modules are collectively allocated globally unique codes. After the general-purpose computing resource pool acquires a resource requirement, a required IO device is configured on the basis of the resource requirement, and a heterogeneous computing resource allocation path is established, so that the general-purpose computing resource pool matches one or more heterogeneous accelerated computing resource pools corresponding to the resource requirement, thereby enabling each general-purpose computing power unit to access any heterogeneous acceleration device, improving the system expansion capability, and improving the operating efficiency of a heterogeneous acceleration server when dealing with large-scale and diversified applications.

The application provides a video rendering method and system based on a computing shader and Xpixmap, compared with an opengl display and a graphics pipeline mode, the computing shader can fully call general computing resources of a GPU, as long as the computing resources are sufficient, high resolution and high frame rate video rendering can be supported, and the processing capacity is greatly improved compared with the graphics pipeline mode. Compared with the opengl display mode, the use of the Xpixmap display mode reduces the multiple copying of the video frame, and further improves the efficiency of the video rendering and display. The scheme fully calls the computing resources of the GPU, renders YUV into RGBA and directly stores in the buffer area corresponding to the Xpixmap, and then uses the X function to submit the display, compared with the opengl display and the graphics pipeline mode, the scheme has higher efficiency, stronger processing capacity and adaptability, and is especially suitable for a graphics processing pipeline with insufficient capacity but powerful general computing capacity.

A device includes a first programmable computing block with an analog content addressable memory array, sense amplifiers, inverters, and a format converter circuit. The array includes analog content addressable memory cells arranged in rows and columns. The format converter circuit is configured to receive a Gray code from the inverters and convert it to a binary code. The device may also include additional programmable computing blocks. A system calculates decimal outputs of a predetermined function for a set of decimal inputs, encodes the outputs into Gray codes, generates mappings associating ranges of the decimal inputs with values for bit positions within the Gray codes, and programs the analog content addressable memory device based on the mappings to directly output the values for the bit positions.

In order to solve the problem in existing low-level I / O peripheral abstraction method for cloud FPGAs that limits flexibility of cloud FPGAs'resource management and tenant usage, this invention introduces an implementation method and system of an FPGA bare metal server, in which the cloud FPGAs are treated as the first-class computing resources in the same manner of the general x86 host. Without customizing and developing new system component, the complexity of managing cloud FPGAs is reduced. Meanwhile, tenants are allowed to directly apply for, deploy and leverage the FPGA bare metal host in a pay-as-you-go manner without applying for additional general computing resources.

The application relates to the technical field of wireless communication, and provides a processor, a chip, a network device and a wireless communication data processing method, wherein the processor comprises: at least one general computing core configured to execute general computing tasks; at least one tensor computing core configured to execute matrix multiplication operation tasks; at least one wireless communication computing core configured to execute preset wireless communication computing tasks; and a shared memory, which is in communication connection with the general computing core, the tensor computing core and the wireless communication computing core, and is configured to be used for data transmission between the computing cores. Through integration of various special computing cores on the processor and adoption of the shared memory architecture, efficient on-chip data interaction between communication computing tasks and AI computing tasks is realized, and the advantages of low delay, high bandwidth and high integration degree are achieved.