GPU-based broadband signal DDC system design method

A system design and broadband signal technology, applied in the direction of program control design, calculation, program startup/switching, etc., can solve the problems of difficult to handle high-speed data, poor scalability, low flexibility, etc., to achieve high throughput, The effect of high flexibility and scalability, high activity rate

Active Publication Date: 2020-08-18
SHANGHAI UNIV
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Problems solved by technology

DDC is the first processing work to be completed after A / D sampling. It is the part with the largest amount of digital processing calculations in the system. Sometimes the sampling rate reaches GHz, and the maximum working rate can only reach a few hundred megahertz. Traditional FPGA processing It is difficult for the server to process high-speed data, and it has the disadvantages of low flexibility and poor scalability

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  • GPU-based broadband signal DDC system design method
  • GPU-based broadband signal DDC system design method
  • GPU-based broadband signal DDC system design method

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Embodiment Construction

[0026] The embodiments of the present invention will be described in further detail below in conjunction with the accompanying drawings, but the present embodiments are not intended to limit the present invention, and any similar structures and similar changes of the present invention should be included in the protection scope of the present invention.

[0027] Such as figure 1 As shown, a GPU-based broadband signal DDC system design method, the specific steps are as follows:

[0028] 1) Receive the sampling signal, the sampling rate is f s , packaged as sr1 according to a fixed duration;

[0029] Described step is specifically as follows: receive the sampling signal that optical fiber transmits, sampling rate is f s , the signal is an Int16 real signal, the signal is packaged according to a fixed duration as sr1, the data length is ILEN, and each packet is continuously received. Here, the double buffering method is used for file transfer management, that is, two buffer poo...

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Abstract

The invention discloses a GPU (Graphics processing unit)-based broadband signal DDC (Direct Down Conversion) system design method, which aims at executing a complex digital signal processing functionin parallel by utilizing a lightweight thread and a kernel of a GPU and mainly completing two tasks, namely digital channelization and sampling rate change. A multiphase filtering digital channelization method is taken as a scheme main body, and a group processing function for broadband acquisition signals is realized, and DDC sampling data is output in parallel in multiple paths. And an efficientresampling method is combined, so that the system is matched with any output sampling rate. According to the GPU-based broadband signal DDC system design method, the powerful general computing powerof the GPU is used; and the parallelism degree of the algorithm is mined, and the algorithm is transplanted to a GPU heterogeneous platform through CUDA programming, and heterogeneous parallel optimization means such as memory optimization, thread organization scheduling optimization and stream processing architecture are adopted, so that the algorithm complexity is effectively reduced, and the scheme has high throughput and high flexibility and adapts to a real-time processing environment.

Description

technical field [0001] The invention relates to a design method of a wideband signal DDC system based on GPU. Designed to take advantage of the GPU's lightweight threads and cores to perform complex signal processing functions in parallel. Background technique [0002] Digital down conversion (Digital down conversion, DDC) is an important module connecting the ADC conversion module and the digital processing system in the software radio technology. The decimation filter restores the original signal, which solves the problem of mismatch between high-speed sampling and low-speed data. DDC is the first processing work to be completed after A / D sampling. It is the part with the largest amount of digital processing calculations in the system. Sometimes the sampling rate reaches GHz, and the maximum working rate can only reach a few hundred megahertz. Traditional FPGA processing It is difficult for the server to process high-speed data, and it has the disadvantages of low flexib...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/50G06F9/48
CPCG06F9/5027G06F9/5038G06F9/4881G06F2209/5018G06F2209/5021
Inventor 刘宝勇刘凯孙霄杰郜婉军
Owner SHANGHAI UNIV
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