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Probe card, wafer testing device and wafer testing method

A wafer testing and probe card technology, which is applied in measuring devices, measuring device casings, electronic circuit testing, etc., can solve the problems that the probe 130 cannot completely contact the wafer, the test accuracy is not high, and errors are easy to occur. , to achieve the effects of easy implementation, improved card replacement efficiency, and increased contact rate

Active Publication Date: 2020-03-24
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

like Figure 1a As shown, it is a side view when the probe card is aligned with the wafer, the wafer is placed above the carrier 110, the probe card 120 is located above the wafer, and its probes 130 face the wafer, and the bonding pads on the wafer need to be aligned. One-to-one correspondence to form an electrical connection, but in the actual alignment process, errors are likely to occur due to manual operations, resulting in a certain angle between the probe card 120 and the wafer in the vertical direction, so that the probes 130 cannot be completely in contact with the wafer. cause test error
like Figure 1b As shown, it is a top view when the probe card is aligned with the wafer, and part of the pads 140 are shown in the figure. In actual operation, due to manual operation, the probe card 120 and the wafer may be displaced by a certain distance in the horizontal direction. , so that the probes cannot all match the pads 140, resulting in test errors
Moreover, when errors exist, it is difficult for human eyes to observe the deviation of the probe card 120, resulting in measurement errors in the above two cases, and the test accuracy is not high

Method used

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  • Probe card, wafer testing device and wafer testing method
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  • Probe card, wafer testing device and wafer testing method

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Embodiment Construction

[0041] Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various figures, identical elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0042] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. Also, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, or region.

[0043] If it is to describe the situation directly on another layer or anothe...

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PUM

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Abstract

The invention discloses a probe card, a wafer testing device and a wafer testing method. The probe card comprises a circuit board; a plurality of first bonding pads located on the circuit board, wherein a plurality of wires are formed among the plurality of first bonding pads; a driving circuit connected with the first bonding pad, wherein a plurality of probes are led out of the driving circuit;second bonding pads positioned on the circuit board and at the peripheries of the plurality of first bonding pads; and a gradienter welded on the second bonding pad, wherein a fault-tolerant ring usedfor representing the maximum allowable offset of the probe card relative to the wafer is marked on the gradienter. The probe card is provided with a bonding pad used for welding a gradienter. Duringtesting, whether the probe card is aligned with the wafer or not is judged by judging whether the bubbles on the gradienter are located in the marked fault-tolerant ring or not, so that the position of the probe card is accurately adjusted, the testing result is more accurate, the replacement frequency of the probe card is reduced, the testing cost is reduced, and the testing efficiency is improved.

Description

technical field [0001] The invention relates to the field of semiconductor testing, in particular to a probe card, a wafer testing device and a wafer testing method. Background technique [0002] The process of semiconductor manufacturing generally includes integrated circuit design, wafer manufacturing, wafer testing, wafer dicing, chip packaging, and finished chip testing. Among them, wafer testing can select chips with functional defects in the wafer in advance to prevent these chips from entering the later chip packaging steps. Wafer refers to the silicon wafer used in the production of silicon semiconductor integrated circuits. Its shape is circular, so it is called a wafer; it can be processed into various circuit element structures on the silicon wafer, and become an IC product with specific electrical functions. . The technical testing of the wafer is very strict, mainly to verify whether the product circuit is good, and whether the function of the driver wafer mee...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R1/073G01R1/067G01R1/04
CPCG01R31/2887G01R31/2891G01R1/073G01R1/06794G01R1/0425
Inventor 朱本强
Owner YANGTZE MEMORY TECH CO LTD