SRAM controller and control method

A control method and controller technology, applied in the SOC field, can solve problems such as bottlenecks, occupancy, and command bandwidth occupation, and achieve low-latency effects

Active Publication Date: 2020-03-24
合肥忆芯电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the granularity of transmission splitting is small, because the cache capacity of the entire channel for commands is limited, it may cause a bottleneck
Moreover, for the currently more common bus structure based on Network On Chip (NOC), since commands and data are packaged and processed, that is, commands occupy one or more shots, followed by one or more shots of data, if If the granularity of transmission splitting is too fine, the actual efficiency of the bus will deteriorate (commands occupy too much bandwidth)

Method used

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  • SRAM controller and control method

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0053] In example 1, in the same clock cycle, each master device does not conflict with the access to SRAM, master device 0 accesses SRAM0, master device 1 accesses SRAM 1, master device 2 accesses SRAM 2, and master device 3 accesses SRAM 3.

[0054]The SRAM access request sent by the master device 0 reaches the bus interface 0 after passing through the bus network. The bus interface 0 sends the SRAM access request to the SRAM interface 0 according to the address specified in the SRAM access request, and the SRAM interface 0 accesses the SRAM 0 according to the SRAM access request. . In a similar manner, bus interface 1 forwards the SRAM access request of master 1 to SRAM interface 1, bus interface 2 forwards the SRAM access request of master 2 to SRAM interface 2, and bus interface 3 forwards the SRAM access request of master 3 Forwarded to SRAM interface 3. SRAM0, SRAM1, SRAM2 and SRAM3 transmit data at the same time, so that the bandwidth of SRAM is fully utilized.

example 2

[0056] In Example 2, in the same clock cycle, two master devices conflict with SRAM access. Both master 0 and master 1 access SRAM 0, master 2 accesses SRAM 2, and master 3 accesses SRAM3.

[0057] The SRAM access request sent by the master device 0 reaches the bus interface 0 through the bus network, and the bus interface 0 sends the SRAM access request to the SRAM interface 0 according to the address specified in the SRAM access request. The SRAM access request sent by the master device 1 reaches the bus interface 1 through the bus network, and the bus interface 1 sends the SRAM access request to the SRAM interface 0 according to the address specified in the SRAM access request. In response to the above two SRAM access requests, SRAM interface 0 selects a SRAM access request (eg, the SRAM access request from bus interface 0 ) within one clock cycle, and accesses SRAM 0 according to the selected SRAM access request. In the next clock cycle immediately adjacent to the above c...

example 3

[0060] In Example 3, in the same clock cycle, three master devices conflict with SRAM access. Master 0, Master 1, and Master 2 all access SRAM 0, and Master 3 accesses SRAM 3.

[0061] The SRAM access request sent by the master device 0 reaches the bus interface 0 through the bus network, and the bus interface 0 sends the SRAM access request to the SRAM interface 0 according to the address specified in the SRAM access request. The SRAM access request sent by the master device 1 reaches the bus interface 1 through the bus network, and the bus interface 1 sends the SRAM access request to the SRAM interface 0 according to the address specified in the SRAM access request. The SRAM access request sent by the master device 2 reaches the bus interface 2 through the bus network, and the bus interface 2 sends the SRAM access request to the SRAM interface 0 according to the address specified in the SRAM access request. SRAM interface 0 selects one SRAM access request (eg, the SRAM acce...

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PUM

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Abstract

The invention discloses an SRAM controller and a control method. The disclosed SRAM controller comprises a plurality of bus interfaces and a plurality of SRAM interfaces. Each bus interface is directly coupled to a main device through a bus network, and each bus interface is coupled to each of all SRAM interfaces; wherein each SRAM interface is coupled to each of all the bus interfaces and is coupled to one SRAM; the bus interface receives an SRAM access request sent by the main equipment from the bus network, and sends the SRAM access request to the corresponding SRAM interface according to aspecified address in the SRAM access request; the SRAM interface responds to one or more SRAM access requests, selects one SRAM access request, and accesses the SRAM according to the SRAM access request.

Description

technical field [0001] The invention relates to the technical field of SOC, in particular to an SRAM controller and a control method. Background technique [0002] SRAM (Static Random Access Memory) is a kind of memory with static access function, which can save the data stored in it without refreshing the circuit. At present, in an SOC (System on Chip, chip-level system), the following methods are usually used to access the SRAM. [0003] In the first way, all master devices (a master device is a device that initiates bus transfer or SRAM access) share the same SRAM controller through an arbiter. [0004] figure 1 It is a system block diagram of a master device accessing an SRAM through an SRAM controller in the prior art. figure 1 Among them, a single SRAM controller is provided, and all master devices share the same SRAM controller through an arbiter. figure 1 The three master devices are coupled to the arbiter, the arbiter is coupled to the SRAM controller, and the S...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16
CPCG06F13/1678
Inventor 徐晓画
Owner 合肥忆芯电子科技有限公司
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