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TIADC system sampling moment mismatch error estimation method based on difference equalization

A technology of sampling time and mismatch error, applied in the direction of analog/digital conversion calibration/test, electrical components, code conversion, etc., can solve the problems of increasing circuit area and power consumption, unsuitable communication system, etc., to achieve good effectiveness, The structure is simple and clear, and the effect is easy to achieve

Active Publication Date: 2020-03-24
SOUTHEAST UNIV
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Problems solved by technology

However, this foreground method needs to interrupt the normal sampling process of TIADC, which is not applicable in many communication systems that require real-time work.
Therefore, some background error estimation algorithms have been proposed to avoid this problem, but some of these background algorithms need to use special auxiliary channels, which will increase the circuit area and power consumption; some background algorithms based on signal autocorrelation operations often need complex The number calculation of the complexity needs to be further optimized

Method used

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  • TIADC system sampling moment mismatch error estimation method based on difference equalization
  • TIADC system sampling moment mismatch error estimation method based on difference equalization
  • TIADC system sampling moment mismatch error estimation method based on difference equalization

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Embodiment 1

[0055] In this embodiment, the four-channel TIADC system model is taken as an example, including the following implementation steps:

[0056] (1) First, the TIADC system of this embodiment is described. This embodiment takes the four-channel TIADC simulation system as an example. The overall sampling rate of the system is 1GS / s, and it is composed of four identical 10bit 250MS / s single-channel ADCs . The initial values ​​of the sampling time mismatch of channels 1, 2, 3, and 4 are set to -10ps, 10ps, 20ps, and -30ps, respectively. The input signal of TIADC is a 171MHz sinusoidal signal with an amplitude of 1Vpp.

[0057] (2) During the TIADC sampling process, the digital domain zero-crossing detection is performed on the output of the ADC of each channel. For the 10bit TIADC of this embodiment, the lower limit of the detection threshold is set to 500, and the upper limit is set to 524.

[0058] (3) For the sampling points filtered out by the zero-crossing detection in the pr...

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Abstract

The invention discloses a TIADC system sampling moment mismatch error estimation method based on difference equalization. The method is used for solving the problem of extraction of inter-channel sampling moment mismatch errors in a TIADC system. A zero-crossing detection unit is arranged in a digital domain, and average absolute difference values output by ADCs of adjacent channels are calculatedand compared at the same time, so that the sampling clock mismatch condition of the ADCs of all the channels can be easily judged. Therefore, the error compensation module can be guided to correct the mismatch at the sampling moment according to the judged mismatch information. The method can achieve the precise estimation of an error caused by the mismatch of a sampling moment in the TIADC, andcan remarkably improve the dynamic performance of a TIADC system. The method is high in estimation speed, is simple in structural design, is not limited by the number of channels, and is very good ineffectiveness, universality and practicality.

Description

technical field [0001] The invention relates to the technical field of high-speed time-interleaving analog-to-digital converters, in particular to a method for estimating mismatch error at sampling time of a TIADC system based on difference equalization. Background technique [0002] High-speed and high-precision analog-to-digital converter (ADC) is an indispensable part of modern broadband communication systems, and is widely used in 4G / 5G wireless base stations, broadband radar and other systems. However, increasing data throughput makes it difficult for single-channel ADCs to meet the design requirements of today's systems. Therefore, a multi-channel time-interleaved analog-to-digital converter (TIADC) emerged as a more effective design choice. [0003] TIADC uses multiple single-channel ADCs to sample circularly, and each channel ADC is driven by a multi-phase clock, so that multiple channel ADCs become a whole TIADC, and the sampling rate is doubled. The design pressu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
CPCH03M1/1071
Inventor 吴建辉李鑫李红
Owner SOUTHEAST UNIV
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