TIADC system sampling moment mismatch error estimation method based on difference equalization
A technology of sampling time and mismatch error, applied in the direction of analog/digital conversion calibration/test, electrical components, code conversion, etc., can solve the problems of increasing circuit area and power consumption, unsuitable communication system, etc., to achieve good effectiveness, The structure is simple and clear, and the effect is easy to achieve
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[0055] In this embodiment, the four-channel TIADC system model is taken as an example, including the following implementation steps:
[0056] (1) First, the TIADC system of this embodiment is described. This embodiment takes the four-channel TIADC simulation system as an example. The overall sampling rate of the system is 1GS / s, and it is composed of four identical 10bit 250MS / s single-channel ADCs . The initial values of the sampling time mismatch of channels 1, 2, 3, and 4 are set to -10ps, 10ps, 20ps, and -30ps, respectively. The input signal of TIADC is a 171MHz sinusoidal signal with an amplitude of 1Vpp.
[0057] (2) During the TIADC sampling process, the digital domain zero-crossing detection is performed on the output of the ADC of each channel. For the 10bit TIADC of this embodiment, the lower limit of the detection threshold is set to 500, and the upper limit is set to 524.
[0058] (3) For the sampling points filtered out by the zero-crossing detection in the pr...
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