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Method for fabricating DMOS transistor

A MOS transistor and double-diffusion technology, applied in the field of manufacturing double-diffusion MOS transistors, can solve the problems of increasing cost tolerance and process complexity, reducing the productivity of electrical qualified devices, etc.

Inactive Publication Date: 2003-05-21
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This patterned mask oxide needs to be etched or removed along with any oxide on the source region without affecting the distribution of the insulating layer above and / or below the gate electrode, which increases cost, tolerance and process complexity. complexity, which results in reduced productivity of electrically qualified devices

Method used

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  • Method for fabricating DMOS transistor
  • Method for fabricating DMOS transistor
  • Method for fabricating DMOS transistor

Examples

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Embodiment Construction

[0027] Detailed description of the preferred embodiment

[0028] The construction and utilization of preferred embodiments of the present invention are disclosed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific situations. Specific embodiments are discussed only in order to illustrate making and using the invention in a particular manner, and not to limit the scope of the invention.

[0029] Next, the production method of the present invention will be described. The best method for fabricating DMOS transistors will be described later.

[0030] see first Figure 2A An insulating region 12 made of a silicon oxide film is provided on the P-type semiconductor substrate 10 . The insulating region 12 is provided for electrically isolating the DMOS elements from each other. Generally, the isolation region 12 composed of a silicon oxide film of a high diele...

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PUM

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Abstract

Disclosed is an improved method for fabricating double-diffused MOS (DMOS) transistors, comprising the steps of thermally oxidizing a previously formed oxide layer on a semiconductor substrate to form a partially and relatively thick oxide layer before performing a POCl3 doping. During the POCl3 doping to render a conductivity to a gate polysilicon layer, phosphorus of the POCl3 can not be penetrated into the substrate through the relatively thick oxide layer. A completed DMOS device has the channel region in the P type body and in the source / drain region which has an ununiform provision of impurity concentration, and results in increase of a withstanding voltage.

Description

technical field [0001] The present invention relates generally to an improved method for fabricating double-diffused MOS (DMOS) transistors, and more particularly to an improved method for fabricating DMOS power transistors, which may be used in discrete or integrated configurations. Background technique [0002] In the future, intelligent power (intelligent power) integrated circuits (ICS) will require high-density power devices, as well as analog functions and VLSI logic devices. The application of DMOS transistors in power devices is very important because it can handle high voltages. One quality factor for such devices is the current capacity handled per unit area or the on resistance per unit area. For a given voltage parameter (rating). The on-resistance per unit area can be reduced by reducing the cell area of ​​the MOS device. [0003] In the field of power transistors, the combined width of the polysilicon and the contact region is defined as the cell pitch of th...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L21/265H01L21/336H01L21/8234H01L27/04H01L29/10
CPCH01L29/66659H01L29/1045H01L21/823425H01L27/04
Inventor 车承峻
Owner SAMSUNG ELECTRONICS CO LTD