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Method for forming semiconductor structure and method for forming silicon oxide film on wafer

A silicon oxide film and semiconductor technology, which is applied in semiconductor/solid-state device manufacturing, gaseous chemical plating, coating, etc., can solve the problem of poor uniformity of the trench 100, affecting the uniformity of etching of the silicon oxide layer 15, and affecting the process And product yield and other issues

Active Publication Date: 2020-03-31
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] like Figures 1b to 1e As shown, along with the etching of each layer of the capacitor structure, the photoresist layer 16 is always warped, which affects the uniformity of the etching of the silicon oxide layer 15, and finally makes the uniformity of the obtained trench 100 worse, specifically as Figure 1e , 1f As shown, thus affecting the subsequent process and product yield

Method used

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  • Method for forming semiconductor structure and method for forming silicon oxide film on wafer
  • Method for forming semiconductor structure and method for forming silicon oxide film on wafer
  • Method for forming semiconductor structure and method for forming silicon oxide film on wafer

Examples

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Effect test

Embodiment 1

[0069] sequentially forming a stacked underlying silicon oxide layer, a first silicon nitride layer, a titanium nitride layer, and a second silicon nitride layer on the substrate;

[0070] The first silicon oxide layer was formed on the second silicon nitride layer by PECVD process, where the RF power was 800W; the reactants used were TEOS and O 2 , O 2 The flow ratio with TEOS is 3:1, and the flow rate of TEOS is 4000sccm.

[0071] A second silicon oxide layer is formed on the first silicon oxide layer by a PECVD process, wherein the reactants used are TEOS and O 2 , O 2 The ratio of flow rate to TEOS is 2.5:1, the flow rate of TEOS is 4000 sccm, and the RF power is adjusted to obtain semiconductor structures with different second silicon oxide layers:

[0072] When the radio frequency power is 1500W, the semiconductor structure S1 is produced;

[0073] When the radio frequency power is 1000W, the semiconductor structure S2 is obtained;

[0074] When the radio frequency ...

Embodiment 2

[0079] sequentially forming a stacked underlying silicon oxide layer, a first silicon nitride layer, a titanium nitride layer, and a second silicon nitride layer on the substrate;

[0080] The first silicon oxide layer was formed on the second silicon nitride layer by PECVD process, where the RF power was 800W; the reactants used were TEOS and O 2 , O 2 The flow ratio with TEOS is 3:1, and the flow rate of TEOS is 4000sccm;

[0081] The second silicon oxide layer was formed on the first silicon oxide layer by PECVD process, where the RF power was 1500W, and the reactants used were TEOS and O 2 , the flow rate of TEOS is 4000sccm, adjust O 2 The flow ratio to TEOS yields semiconductor structures with different second silicon oxide layers:

[0082] o 2 When the flow ratio with TEOS is 5:1, the semiconductor structure S4 is obtained;

[0083] o 2 When the flow ratio with TEOS is 3:1, the semiconductor structure S5 is obtained;

[0084] o 2 When the flow ratio with TEOS is...

Embodiment 3

[0089] On the substrate, sequentially form a stacked underlying silicon oxide layer, a first silicon nitride layer, a titanium nitride layer, and a second silicon nitride layer; adjust the radio frequency power, O 2 The flow ratio to TEOS yields semiconductor structures with different surface silicon oxide layers:

[0090] A 200nm silicon oxide layer was formed on the second silicon nitride layer by PECVD process, where the RF power was 1500W; the reactants used were TEOS and O 2 , O 2 The flow ratio to TEOS was 5:1, resulting in the semiconductor structure S6.

[0091] A 200nm silicon oxide layer was formed on the second silicon nitride layer by PECVD process, where the RF power was 700W; the reactants used were TEOS and O 2 , O 2 The flow ratio to TEOS was 2:1, resulting in semiconductor structure D4.

[0092] The semiconductor structures S6 and D4 were tested by FTIR respectively. For specific spectra, see Figure 7 .

[0093] Figure 5 to Figure 6 Be the infrared sp...

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Abstract

The invention provides a method for forming a semiconductor structure and a method for forming a silicon oxide film on a wafer. The method for forming the semiconductor structure comprises the following steps: forming a first silicon oxide layer on a substrate; and forming a second silicon oxide layer on the first silicon oxide layer by adjusting the radio frequency power and the flow ratio of thedeposition process, wherein the radio frequency power is 800-1500 W, the flow ratio is the flow ratio of oxygen to silicide, and the flow ratio is (3-5): 1. By adjusting the radio frequency power andthe flow ratio of the deposition process, the surface of the semiconductor structure has low-H and-OH content, a hydrophobic surface is further formed, and the hydrophobic surface can improve the adhesion between the semiconductor structure and the photoresist.

Description

technical field [0001] The invention relates to a semiconductor structure, in particular to a method for forming a semiconductor structure with low content of -H and -OH on the surface. Background technique [0002] State-of-the-art deposited SiO 2 film, due to the presence of H(SiH 4 , TEOS, etc.) cause the surface of the grown film to contain -H and -OH, thereby making the surface of the film hydrophilic. The hydrophilic surface is not suitable for photoresist bonding. When etching deep grooves, due to long-term plasma bombardment, the contact surface between photoresist and film may appear photoresist warping due to poor adhesion. , resulting in poor uniformity of etched line width. [0003] Figure 1a It is a schematic diagram of an existing capacitor structure. According to the direction shown in the figure, the capacitor structure includes silicon oxide (SiO 2 ) layer 11, silicon nitride (SiN) layer 12, titanium nitride (TiN) layer 13, silicon nitride (TiN) layer 1...

Claims

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Application Information

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IPC IPC(8): H01L21/02C23C16/40
CPCH01L21/02164H01L21/02274C23C16/402
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC