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Chip stacking and packaging method and packaging structure

A technology of chip stacking and packaging methods, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., and can solve the problems of low production yield of chip packaging structures, increased preparation costs of chip stacking packaging structures, and many unqualified finished products, etc. problem, to achieve the effect of reducing implementation difficulty, high yield, and reducing production cost

Inactive Publication Date: 2020-04-10
江苏中科智芯集成科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Therefore, the technical problem to be solved by the present invention is to solve the problem that the existing chip stacking packaging structure preparation process may produce more unqualified finished products, resulting in a lower production yield of the chip packaging structure and an increase in the preparation cost of the chip stacking packaging structure. question

Method used

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  • Chip stacking and packaging method and packaging structure
  • Chip stacking and packaging method and packaging structure
  • Chip stacking and packaging method and packaging structure

Examples

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Embodiment 1

[0039] This embodiment provides a fan-out chip stack packaging method, such as figure 1 As shown, the packaging structure method includes the following steps:

[0040] S101: Prepare the first stacking module 1 .

[0041] here, as figure 2 As shown, the first stack module 1 includes a first chip 11, a first package body 12 and a first stack connector 13, wherein the first package body 12 encapsulates the first chip 11, and the first stack connector 13 is also arranged on In the first package 12, one end of the first stack connector 13 is coupled to the first chip 11, and the other end is exposed to the first package through a groove 14 corresponding to the first stack connector 13 in the first package. A package body 12 outside.

[0042] Here, the first chip 11 is a general term for all the chips in the first stacked module 1, specifically, the first chip 11 can be one chip or multiple chips, and when the first chip 11 is multiple chips, The plurality of chips may be of th...

Embodiment 2

[0089] This embodiment provides a chip stack packaging structure, and the chip stack packaging structure can be prepared according to the chip stack packaging method and its preferred implementation in Embodiment 1, and what has already been described will not be repeated.

[0090] The chip stack package structure provided by the embodiment of the present invention, such as Figure 4 As shown, it includes: a first stacking module 1 and a second stacking module 2 .

[0091] Wherein, the first stack module 1 includes a first chip 11 , a first package body 12 and a first stack connector 13 . Specifically, the first package 12 encapsulates the first chip 11, and one end of the first stack connector 13 is coupled to the first chip 11, and the other end is connected to the first stack connector 13 through the first package. The corresponding groove 14 is exposed outside the first package body 12 . The second stack module 2 includes a second chip 21, a second package body 22 and a ...

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Abstract

The invention discloses a chip stacking and packaging method and a packaging structure. The method comprises: a first stacking module is prepared, wherein the first stacking module comprises a first chip, a first packaging body and a first stacking connecting piece; the first packaging body packages the first chip, the first stacking connecting piece is arranged in the first packaging body, one end of the first stacking connecting piece is coupled with the first chip, and the other end of the first stacking connecting piece is exposed out of the first packaging body through a groove, corresponding to the first stacking connecting piece, in the first packaging body; a second stacking module is prepared; the second stacking module comprises a second chip, a second packaging body and a secondstacking connecting piece; the second packaging body packages the second chip, one end of the second stacking connecting piece is coupled with the second chip, and the other end of the second stacking connecting piece extends in the direction away from the second chip; and the second stacking connecting pieces are coupled to the corresponding first stacking connecting pieces through the grooves.By implementing the method, the preparation cost of the chip stacking and packaging structure can be reduced, and the yield of products is improved.

Description

technical field [0001] The invention relates to the technical field of packaging of semiconductor integrated circuits, in particular to a chip stack packaging method and packaging structure. Background technique [0002] At present, the chip stacking method mostly adopts the wire bonding (wire bond) or flip chip (Flip chip) packaging method of the redistribution substrate: firstly, a pad is reserved on the bottom substrate or a via hole is penetrated through the plastic film, and then the upper layer The packaged chip adopts wire bond (WB for short) or Flip-Chip (FC for short) or a combination of the two to realize the connection between the upper and lower chips. However, due to the existence of the substrate, the height of the stacked package becomes high, which limits its application in ultra-thin electronic products. Therefore, in order to solve this problem, the industry has proposed chip stack packaging methods based on fan-out packaging (Fan-out) and embedded laminat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/485H01L23/31H01L21/56
CPCH01L21/56H01L23/3128H01L24/02H01L24/03H01L2224/02331H01L2224/02379H01L2224/02381H01L2224/03H01L2224/16225H01L2224/18
Inventor 姚大平
Owner 江苏中科智芯集成科技有限公司
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