Multiplication unit circuit utilizing threshold voltage characteristics and multiplier

Abstract

The invention discloses a multiplication unit circuit utilizing threshold voltage characteristics and a multiplier. The multiplication unit circuit is composed of two exclusive-OR gates, four NAND gates and four inverters. The multiplier is composed of a plurality of multiplication unit circuits. The exclusive-OR gate and the NAND gate are used as two basic units of the multiplication unit circuit, and are achieved by adopting the same circuit structure; when the threshold voltage characteristics of the MOS tubes in the same circuit structure are configured, the circuit structure can respectively realize an exclusive-OR logic function and an NAND logic function; the multiplication unit circuit achieves one-time evaluation operation in one period, the period is divided into three stages, namely a pre-charging stage, an evaluation operation stage and a discharging stage, and differential pull-down networks of an exclusive-OR gate and an NAND gate are each of a single-ended structure. Themultiplication unit circuit has the advantages that the area and the power consumption overhead are small, reverse engineering and DPA attacks can be defended at the same time, and the safety is high.

Description

technical field [0001] The invention relates to a multiplication unit circuit, in particular to a multiplication unit circuit and a multiplier utilizing threshold voltage characteristics. Background technique [0002] With the development of VLSI and information security technology, the protection of intellectual property (Intellectual Property, IP) has received more and more attention. At the same time, there are endless ways to attack the chip IP core. Reverse engineering is currently one of the ways for attackers to quickly master the core technology of the designer's chip. The attacker analyzes the internal structure of the chip through reverse engineering, extracts the circuit netlist, and grasps the actual function of the chip, which seriously affects the legitimate interests of the designer. Chip cloning and other behaviors seriously infringe the intellectual property rights of the designer. For the encryption chip, the attacker bypasses the cryptographic algorithm ...

AI Technical Summary

Problems solved by technology

In terms of multiplier implementation, multipliers based on adiabatic dynamic differential logic have certain deficiencies in security, are vulnerable to reverse engineering and DPA attacks, and the timing control is complex, and complex interface circuits need to be designed when interacting with CMOS circuits , the circuit structure is complex, and the area and power consumption are large; although the multiplier implemented by the differential logic based on the lookup table has good anti-DPA attack performance, it cannot be defended against reverse engineering, and it requires more transistors, and the area and power consumption The overhead is also high; the output load capacitance of the multiplier based on sensitive amplification logic is not completely consistent, and it may still be used as a breakthrough point for reverse engineering and DPA attacks

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