Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

LED chip and preparation method thereof

A technology of LED chips and insulating layers, which is applied in the direction of electrical components, circuits, semiconductor devices, etc., can solve the problems of loss of luminous area, insulation problems of hole walls, and reduction of light efficiency, so as to achieve good application prospects, relieve current congestion, and improve the preparation process. simple effect

Inactive Publication Date: 2020-04-28
SOUTH CHINA UNIV OF TECH
View PDF7 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The size of the diffusion range is limited by the conductivity of the n-GaN layer, which is often only about 100um. To achieve uniform current expansion across the entire surface, it is necessary to increase the hole density to compensate for the limitation of the diffusion distance. However, the increase in the hole density will cause loss Losing more light-emitting area and reducing light efficiency is not worth the candle
At the same time, the problem of hole wall insulation caused by the increase in the number of holes is also more serious

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • LED chip and preparation method thereof
  • LED chip and preparation method thereof
  • LED chip and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0042] A kind of LED chip, refer to figure 1 As shown, it includes conductive substrate 01, n-electrode contact layer 02, first insulating layer 03, p-contact mirror metal and protective layer 04, ring-shaped CBL layer 05, and p-type GaN layer 06 arranged in order from bottom to top , InGaN / GaN multi-quantum well light-emitting layer 07, n-type GaN layer 08, second insulating layer 09, and P electrode 10; the embedded columnar N electrode layer 02 radially penetrates the first insulating layer 03, p-contact mirror in sequence The metal and protective layer 04, the annular CBL layer 05, the p-type GaN layer 06, and the InGaN / GaN multi-quantum well light-emitting layer 07 form a columnar embedded n-electrode layer, which is finally in contact with the n-type GaN layer 08; the embedded columnar N The electrode layer 02 is connected to the conductive substrate 01 to form electrical conduction; the upper surface of the columnar embedded n-electrode layer is connected to n-GaN08 to ...

Embodiment 2

[0060] This embodiment provides an LED chip (LED-2). The difference from the chip of Embodiment 1 is mainly reflected in the structure of the CBL layer. The CBL layer of this embodiment is not a substantial material structure, but a P-GaN surface Corresponding positions of the passivation area are subjected to selective dimension etch strokes.

[0061] Correspondingly, in the preparation method of this embodiment, the preparation process of the CBL layer is a photolithography plus ICP etching process and a CBL ring structure. ICP etch using H 2 / Ar, ratio 8:1, upper power 160W lower power 70W, etching time 2min.

[0062] Other structures and methods are completely consistent with Example 1.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
thicknessaaaaaaaaaa
Login to View More

Abstract

The invention discloses an LED chip and a preparation method thereof. The LED chip comprises a conductive substrate, an n electrode contact layer, a first insulating layer, a p contact reflector metaland protective layer, annular CBL layers, a p-type GaN layer, an InGaN / GaN multi-quantum well light-emitting layer, an n-type GaN layer and a second insulating layer which are sequentially arranged and distributed from bottom to top. Embedded columnar N electrode layers are respectively inserted into a bonding metal layer and sequentially penetrate through the first insulating layer and the like;and the upper surface of each embedded columnar N electrode layer is connected with the n electrode contact layer to form ohmic contact. According to the LED chip provided by the invention, current distribution optimization can be realized by utilizing the design of the CBL layers around holes under the condition that the number of electrode holes is not increased, namely, the light-emitting areais not lost, and the brightness of the chip is further improved.

Description

technical field [0001] The invention relates to the technical field of LED manufacturing, in particular to an LED chip and a preparation method thereof Background technique [0002] With the gradual application of LED in the field of lighting, the market has higher and higher requirements for the light efficiency of white light LED. The demand for super-sized LED chips is becoming more and more mainstream. The first problem faced by ultra-high power and ultra-large-sized LEDs is the current crowding. Higher power requirements pose a greater challenge to the current expansion capability of LED chips. Ordinary vertical structures can no longer meet the design requirements of higher power chips such as 5W and above (Yu Binhai, Wang Hao. Junction temperature and Thermal resistance restricts the development of high-power LED [J]. Chinese Journal of Luminescence, 2005,26(6):761-766.). The LED chip with an embedded electrode structure extends the N electrode into the n-GaN throu...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L33/14H01L33/38H01L33/00
CPCH01L33/0066H01L33/0075H01L33/145H01L33/382H01L33/387H01L2933/0016
Inventor 李国强陈曦午柴华卿林志霆
Owner SOUTH CHINA UNIV OF TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products