Shallow trench isolation structure and forming method thereof

Abstract

The invention relates to a shallow trench isolation structure and a forming method thereof, and relates to the manufacturing process of semiconductor integrated circuits. In the shallow trench isolation structure, a silicon nitride layer is formed on the surface of a lining oxide layer, and due to the fact that the silicon nitride layer is hard in material and high in injection resistance, the bombardment force of source and drain injection on the side wall of an active region can be weakened, dislocation is reduced, and finally the leakage current characteristic of a device is improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing process, in particular to a shallow trench isolation structure and a forming method thereof. Background technique [0002] As the feature size of semiconductor devices continues to shrink, the isolation area between devices must also be reduced accordingly. Shallow trench isolation (STI: shallow trench isolation) technology is a commonly used isolation technology at present, especially in deep submicron processes below 0.35 microns. Although STI technology has been widely used in mass production, there is still much work to be done on how to improve the morphology of STI to obtain ideal leakage characteristics and good narrow channel effect. It has been proved by practice that the corner shape of the STI has a great influence on the overall performance of the device. In order to obtain a good STI shape, an STI lining oxide layer (Liner OX) can be used to obtain an ideal STI sha...

AI Technical Summary

Problems solved by technology

In low-capacity or non-low-power SRAM circuits, the SRAM static leakage current level caused by dislocations accounts for only a small part of the maximum allowable leakage current, but at the same time, the improvement of its process also encounters a bottleneck

However, in 16M low-power SRAM circuits with 90nm or 65nm process, the static leakage current caused by dislocations becomes the main component of the total leakage current, causing the leakage current to exceed the specification and greatly reducing the SRAM yield

Among them, the bombardment of source-drain ion implantation is an important reason for generating dislocations in the active region. Due to the different crystal orientations, at the STI corner position, after the STI inner layer oxidation process, the stress is relatively concentrated, and the source-drain implantation is easy to pass through the STI lining oxidation process. layer, bombards the sidewalls of the active region, causing dislocations at the bottom

The generation of dislocations can be reduced by reducing the source-drain ion implantation energy, but the side effect is to increase the resistance of the active region

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